microwatt

Author	SHA1	Message	Date
Anton Blanchard	15bb4aa90a	First pass at an external JTAG port The verilator simulation interface uses the remote_bitbang protocol from openocd. I have a simple implementation for urjtag too. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Anton Blanchard	8acd5a5607	verilator: Specify top level module While verilator finds the correct top level module with the current setup, if we start adding simulation models it can get confused. Explicitly specify the top level module. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Anton Blanchard	04c56a0c52	Pass clock frequency to UART sim wrapper The UART sim wrapper is currently hard wired to 50 MHz. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	3e8a6a8fc2	Add yosys/verilator support Add a microwatt-verilator target that simulates the ghdl -> yosys -> verilog -> verilator path. A good test of ghdl/yosys synthesis. Because the everything is run through synthesis, the instruction image is baked into the build via the RAM_INIT_FILE generic. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago