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fpu-init
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dcache-unused-sig
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divider-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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1 Commits (6427cab46fe7f37074505e18a1957414023c2708)

Author SHA1 Message Date
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago