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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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3 Commits (6692f0db4f0eaff8bbb5d493cde64b9a2add3d64)

Author SHA1 Message Date
Benjamin Herrenschmidt c5f5f50738 hello_world: Use new headers and frequency from syscon 
This uses the new header files for register definitions and
extracts the core frequency from syscon rather than hard coding it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Paul Mackerras 04ec2115ad hello_world: Use ldcix/stdcix to access UART 
This is one step towards ultimately removing the address-based
cache inhibit hack from dcache.vhdl.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Anton Blanchard 75f3614776 hello_world updates 
Shrink hello_world a bit (from 12kB to 8kB).
Include the built images
Add 0x10 and 0x100 entry points

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago