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fpu-init
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icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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2 Commits (6701e7346b598f97100f609956a4b9df282af6f7)

Author SHA1 Message Date
Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations 
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 6fe077910b litedram: Add simulation support 
This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago