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fpu-init
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divider-init
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alt-reset-address
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asic-3
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orange-crab-freq
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remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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jtag-port-2
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1 Commits (6e1e763c025fb72707275f1aca0bb55fb9fc2f0d)

Author SHA1 Message Date
Matt Johnston a9b467f43b orangecrab: add Orange Crab r0.2 target 
top-orangecrab0.2 is a copy of top-arty with various changes.
USRMCLK is added for the SPI clock
ethernet is removed

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 2 years ago