3 Commits (7577cb18fbd92ee3f5acad9084e4fe700092255a)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	a93d9e77c9	litedram: Remove remnants of riscv-inits ... We still had some wires bringing an extra serial port out of litedram for the built-in riscv processor. This is all gone now so take them out. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	b0e15f2fb5	litedram: Make the L2 twice as tall ... This increases the number of L2 lines from 32 to 64. The BRAM usage is the same as they were only half used. There's an increase in LUTs and registers due to the extra tags and valid bits, but none of it should be in a space constrained or critical timing path. We could make it wider instead (256 bytes lines) which would reduce usage instead, but this increases the latency by 8 cycles. Something to consider once the L2 is capable of early response on miss and starting reloads from any point in a line. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	599fad117b	litedram: Remove old "VexRiscV" based initializations ... Support for this has bitrotted and would require refactoring of L2 to be brought back. It's also not really needed anymore now that we ship pre-generated litedram and that LiteX supports what we do. So take it out, which simplifies some of the scripts as well. This also fixes up CSR alignment the sim model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago