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fpu-init
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core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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3 Commits (7b054363c282711671c6292ecf987eb0c66be1ea)

Author SHA1 Message Date
Anton Blanchard 7b054363c2 First pass at an external JTAG port 
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 04c56a0c52 Pass clock frequency to UART sim wrapper 
The UART sim wrapper is currently hard wired to 50 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support 
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago