Commit Graph

3 Commits (7c2a2b7414d7dd166f297d316cb60ef88ccdb8d3)

Author SHA1 Message Date
Anton Blanchard 021d427d3f Stores need to wait for wishbone write ack
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling 4d5abfb430 Remove dynamic ranges from code
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago