matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,073 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '7da4977028'
${ noResults }
Commit Graph

7 Commits (7da4977028296402545e554420bf276fa950443a)

Author SHA1 Message Date
Anton Blanchard 7da4977028 Disable FPU 3 years ago
Anton Blanchard 1383bbb8be Add GPIOs 3 years ago
Anton Blanchard 46a85cb274 Add asic alternate reset address 3 years ago
Anton Blanchard 4e9001ba19 Hook up JTAG to asic top level 3 years ago
Anton Blanchard 18503732d7 Add ASIC target 3 years ago
Anton Blanchard 5ac715d932 Fix multiplier behavioural 3 years ago
Anton Blanchard 537a0aac1d Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago