58 Commits (88b28a7b178cf8c4d611725021862035629fbbcd)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	3ac1dbc737	Share soc.vhdl between FPGA and sim ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	8bfd6e5eae	Use simulated UART in core test bench ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	03fd06deaf	Rework SOC reset ... The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5e140298a5	Rework decode2 ... The decode2 stage was spaghetti code and needed cleaning up. Create a series of functions to pull fields from a ppc instruction and also a series of helpers to extract values for the execution units. As suggested by Paul, we should pass all signals to the execution units and only set the valid signal conditionally, which should use less resources. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	f98370f9e6	Merge pull request #5 from antonblanchard/travis-test ... Add an initial travis.yml	5 years ago
Anton Blanchard	2ee269abdb	Add an initial travis.yml ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	96787091a6	Add -Wall to CFLAGS ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago