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fpu-init
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dcache-unused-sig
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divider-init
loadstore-pmu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
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remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
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1 Commits (893d2bc6a24f9d1dbae374e7aa01b2abda57d140)

Author SHA1 Message Date
Benjamin Herrenschmidt 6828e93113 litedram: Test bench 
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 4 years ago