2 Commits (8bb3c8f8b6e71935cf9acceaa2139f6d68024975)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	982cf166dd	litedram: Add basic support for LiteX LiteDRAM ... This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	fe275effeb	New C based JTAG debug tool ... This works with both the sim socket and urjtag, and supports the new core functions, loading a file in memory etc... The code still needs a lot of cleanup and a help! Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago