Commit Graph

5 Commits (9ec22af256ec1102dd34f8f23a38fbf71e5147f2)

Author SHA1 Message Date
Paul Mackerras ca4eb46aea Make wishbone addresses be in units of doublewords or words
This makes the 64-bit wishbone buses have the address expressed in
units of doublewords (64 bits), and similarly for the 32-bit buses the
address is in units of words (32 bits).  This is to comply with the
wishbone spec.  Previously the addresses on the wishbone buses were in
units of bytes regardless of the bus data width, which is not correct
and caused problems with interfacing with externally-generated logic.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
3 years ago
Benjamin Herrenschmidt 079af6443e litedram: Update generator to work with latest LiteX
Some changes in LiteX broke us. Adapt the build system and
increase the init RAM size to 24KB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 63f10450a6 litedram: Fix DRAM init mem using too many address bits
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 12f36b4a35 litedram: Split the init memory from the main wrapper
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago