microwatt

Commit Graph

Author	SHA1	Message	Date
Paul Mackerras	a27ed0ec27	wishbone_debug_master: Improve timing The current code has the possibility that we could set reg_addr or reg_ctrl and then increment reg_addr in the same cycle, resulting in some long timing paths. Rearrange the code to make it clear that we are not trying to add an auto-increment to data from outside the module; in any given cycle we either set one of reg_addr and reg_ctrl, or we possibly increment reg_addr. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago
Benjamin Herrenschmidt	b46f81fae4	Wishbone debug module This adds a debug module off the DMI (debug) bus which can act as a wishbone master to generate read and write cycles. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Paul Mackerras

a27ed0ec27

wishbone_debug_master: Improve timing

The current code has the possibility that we could set reg_addr
or reg_ctrl and then increment reg_addr in the same cycle, resulting
in some long timing paths.  Rearrange the code to make it clear
that we are not trying to add an auto-increment to data from
outside the module; in any given cycle we either set one of
reg_addr and reg_ctrl, or we possibly increment reg_addr.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

Benjamin Herrenschmidt

b46f81fae4

Wishbone debug module

This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 Commits (a0d95e791e52b1ca7ee7b14e041453fb54e34a6f)