microwatt

Commit Graph

Author	SHA1	Message	Date
Benjamin Herrenschmidt	573b6b4bc4	soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	f96d179f66	Some yosys fixes This gets the yosys build further along, but I'm now chasing what looks like a yosys bug. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Benjamin Herrenschmidt	3ac815823c	fpga: Hookup Arty to litedram The old toplevel.vhdl becomes top-generic.vhdl, which is to be used by platforms that do not have a litedram option. Arty has its own top-arty.vhdl which supports litedram and is now hooked up Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago

Author

SHA1

Message

Date

Benjamin Herrenschmidt

573b6b4bc4

soc: Rework interconnect

This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Anton Blanchard

f96d179f66

Some yosys fixes

This gets the yosys build further along, but I'm now chasing what looks
like a yosys bug.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Benjamin Herrenschmidt

3ac815823c

fpga: Hookup Arty to litedram

The old toplevel.vhdl becomes top-generic.vhdl, which is to be used
by platforms that do not have a litedram option.

Arty has its own top-arty.vhdl which supports litedram and is now
hooked up

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

3 Commits (a9178ed0c151e6096e378777f31739556e0eeb9b)