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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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13 Commits (a93d9e77c9cdc69e6e98ceaf12d2c73dcd22230e)

Author SHA1 Message Date
Anton Blanchard 6326efaca4 Add Makefile command line variables to enable docker and podman 
Instead of having to edit the Makefile, we can now do:

make DOCKER=1
make PODMAN=1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Paul Mackerras cf4dfeca36 Change the default cross compiler prefix to powerpc64le-linux-gnu- 
That is what is used by the packaged cross-compilers on (at least)
Fedora and Ubuntu.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Joel Stanley 04b784011a README: hello world needs 16KB of RAM 
STACK_TOP is at 0x2000 (8K) so we need something larger as a minimum.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 5 years ago
Anton Blanchard 5f2efde644 Add some information about GHDL backend issues 
A number of people have tripped up on GHDL backend issues. We
require either the LLVM or gcc backend, because the mcode backend
can't link against libraries which we use for simulated memory
and UART. Make that clearer, and point people at the Docker images
if they are having issues building ghdl.

Also point at the prebuilt micropython image.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 1aec1a4b0e Point to upstream micropython 
Our changes are now merged upstream, so point there instead.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Dan Horák f552021d19 document packaged fusesoc for Fedora users 
Signed-off-by: Dan Horák <dan@danny.cz>
 5 years ago
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Hugh 96b7f17e52 Minor tweaks to README.md 
Few tweaks based on a newcomers experience getting an Arty A7-100 up and running

Forgot to add DCO in initial PR, now corrected.

Signed-off-by: Hugh Blemings <hugh@blemings.org>
 5 years ago
Cameron Kaiser 07d3c8e4de Add logo to README.md 
Signed-off-by: Cameron Kaiser <classilla@floodgap.com>
 5 years ago
Anton Blanchard c8328cdf84 Remove gcc software divide patch 
We have a divider, thanks to Paul.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md 
Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard 77f1588a7f Add some initial FPGA synthesis instructions 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago