4 Commits (ad1c8e7e141ebac06802c71d4c1691aea1b0c8be)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	7560e8f2ff	arty/nexys: Rework reset with litedram ... When using litedram, request a much longer PLL reset. This seems to help get rid of all the grabled output after config. Also use the clean system_rst out of litedram as our source of reset for the rest of the SoC (it is synchronized with system_clk and takes pll_locked into account already)	5 years ago
Benjamin Herrenschmidt	c19b5b8cc7	litedram: Update to new LiteX/LiteDRAM version ... Things have changed a bit in upstream LiteX. LiteDRAM now exposes a wishbone for the CSRs for example. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	025cf5efe8	syscon: Add syscon registers ... These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	2cef3005cd	fpga: Hookup nexys-video to litedram ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago