Commit Graph

3 Commits (cc27e239f4e78d2dc0f9c847aeb3df4358e627a9)

Author SHA1 Message Date
Michael Neuling e5a30a1358 Wire up sim uart TX interrupt
TX is always ready, so just always sent interrupt when enabled.

No RX interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt 48b689b665 Add simulated UART design
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>