3 Commits (e6536d4b8bf93cdb5456b6cd97cfbc4ebc41f34c)

Author	SHA1	Message	Date
Paul Mackerras	e6536d4b8b	divider: Always compute result/sresult/d_out.write_reg_data ... These are intended to be combinatorial. The previous code was giving warnings in vivado about registers/latches with no clock defined. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	6 years ago
Paul Mackerras	a01ffaeb64	Speed up the divider a little ... This looks for cases where the next 8 bits of the quotient are obviously going to be zero, because the top 72 bits of the 128-bit dividend register are all zero. In those cases we shift 8 zero bits into the quotient and increase count by 8. We only do this if count < 56. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	6 years ago
Paul Mackerras	d5bc6c8824	Add a divider unit and a testbench for it ... This adds a divider unit, connected to the core in much the same way that the multiplier unit is connected. The division algorithm is very simple-minded, taking 64 clock cycles for any division (even 32-bit division instructions). The decoding is simplified by making use of regularities in the instruction encoding for div* and mod* instructions. Instead of having PPC_* encodings from the first-stage decoder for each of the different div* and mod* instructions, we now just have PPC_DIV and PPC_MOD, and the inputs to the divider that indicate what sort of division operation to do are derived from instruction word bits. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	6 years ago