microwatt

Author	SHA1	Message	Date
Benjamin Herrenschmidt	ee52fd4d80	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Michael Neuling	83d773090e	Fix verific script with new VHDL files This really needs to be auto generated, but here we are. Signed-off-by: Michael Neuling <mikey@neuling.org>	6 years ago
Michael Neuling	4d5abfb430	Remove dynamic ranges from code Some VHDL compilers like verific [1] don't like these, so let's remove them. Lots of random code changes, but passes make check. Also add basic script to run verific and generate verilog. 1. https://www.verific.com/ Signed-off-by: Michael Neuling <mikey@neuling.org>	6 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago