microwatt

Commit Graph

Author	SHA1	Message	Date
Matt Johnston	42959184dd	litesdcard: add lattice, regenerate Modifies litescard generate script to take a clock speed. Regenerated verilog with latest litesdcard e52c731 ("Bump year.") Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>	3 years ago
Anton Blanchard	9caaa3fc46	litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Paul Mackerras	21ed730514	arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	4 years ago

Author

SHA1

Message

Date

Matt Johnston

42959184dd

litesdcard: add lattice, regenerate

Modifies litescard generate script to take a clock speed.

Regenerated verilog with latest litesdcard
e52c731 ("Bump year.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>

Anton Blanchard

9caaa3fc46

litesdcard: Use vendor not board type

litesdcard provides a macro per vendor (eg xilinx, lattice) and not per
board, so modify the fusesoc generator to take a vendor. This will make
it easier to add litesdcard to more boards.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Paul Mackerras

21ed730514

arty_a7: Add litesdcard interface

This adds litesdcard.v generated from the litex/litesdcard project,
along with logic in top-arty.vhdl to connect it into the system.
There is now a DMA wishbone coming in to soc.vhdl which is narrower
than the other wishbone masters (it has 32-bit data rather than
64-bit) so there is a widening/narrowing adapter between it and the
main wishbone master arbiter.

Also, litesdcard generates a non-pipelined wishbone for its DMA
connection, which needs to be converted to a pipelined wishbone.  We
have a latch on both the incoming and outgoing sides of the wishbone
in order to help make timing (at the cost of two extra cycles of
latency).

litesdcard generates an interrupt signal which is wired up to input 3
of the ICS (IRQ 19).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

3 Commits (ee5e3778edc1d6234195d746236e3804f682a9cf)