4 Commits (ef01fa32bd888215ffc688389296f17676667590)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	079af6443e	litedram: Update generator to work with latest LiteX ... Some changes in LiteX broke us. Adapt the build system and increase the init RAM size to 24KB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	6aadad5a75	spi: Add booting from flash to litedram init ... It will look for an ELF binary at the flash offset specified for the board (currently 0x300000 on Arty but that could be changed). Note: litedram is regenerated in order to rebuild the init code, which was done using a newer version of litedram from LiteX. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	573b6b4bc4	soc: Rework interconnect ... This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago
Benjamin Herrenschmidt	982cf166dd	litedram: Add basic support for LiteX LiteDRAM ... This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	6 years ago