Commit Graph

5 Commits (f384f504a1a97317f5697d3ad6c91240940642d4)

Author SHA1 Message Date
Anton Blanchard 03fd06deaf Rework SOC reset
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard a53ad60014 Rename a few reset signals
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Olof Kindgren e8ad9bed10 Expose ram init file and memory size through toplevel 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago