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fpu-init
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dcache-unused-sig
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divider-init
loadstore-pmu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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1 Commits (f3f159c6dc2b2759639c48855d542f4c593ecd5e)

Author SHA1 Message Date
Paul Mackerras e7a08f33eb tests: Add a test for the load-reserve and store-conditional instructions 
This checks that the instructions seem to update memory as expected,
and also that they generate alignment interrupts when necessary.
We don't check whether the memory update is atomic as we don't have
SMP yet.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago