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24 Commits

Author SHA1 Message Date
Anton Blanchard f3f159c6dc Check in verilog 2 years ago
Anton Blanchard 4a7844404e Forgot to add DFFRAM 2 years ago
Anton Blanchard 6f697e4f5f Update PVR 2 years ago
Anton Blanchard 9910d99320 Not sure we need this 2 years ago
Anton Blanchard 9ccf9a7f80 Add a script to post process the microwatt verilog for caravel 2 years ago
Jordan Niethe a45c503aea Connect to the caravel logic analyzer 2 years ago
Anton Blanchard ce27cd3e28 Disable debug log 2 years ago
Anton Blanchard 5326455c02 No need to set HAS_FPU and LOG_LENGTH in Makefile 2 years ago
Anton Blanchard bf0c08dd87 tie off wb_ext_io_out 2 years ago
Anton Blanchard 120e1ce6ec SPI fixes, and remove reset controller and PLL 2 years ago
Michael Neuling 0664747146 Set alt reset vector to the start of flash at 0xf0000000 and make it 2 years ago
Michael Neuling 4685ff6bbb Add mc*.vhdl from: 2 years ago
Anton Blanchard 185bcba6bb Add a simple test case 2 years ago
Anton Blanchard 83faae4a86 Add RAM_512x64 2 years ago
Anton Blanchard d1f0ac2e0b Disable second uart since we aren't using it 2 years ago
Anton Blanchard 17d93d504a Add a toplevel file for caravel 2 years ago
Anton Blanchard 9877db9b97 Disable BOOT_CLOCKS in flash controller 2 years ago
Anton Blanchard d852dedfe4 Reduce the core size 2 years ago
Anton Blanchard 7fdbb7c850 Cut down hello_world to fit in 4kB 2 years ago
Michael Neuling 1ee4995cd8 Cleanup some 'U' state issues 2 years ago
Anton Blanchard 55b6f8be52 Work around ghdl/yosys issue with direct mapped TLB 2 years ago
Anton Blanchard 0be86c3a32 Update JTAG TAP controller for Microwatt 2 years ago
Anton Blanchard 5e8ba5acb0 First pass at an external JTAG port 2 years ago
Anton Blanchard a3b70ab01e Reset cmd_ready_o in spi_txrx 2 years ago
  1. 23
      Makefile
  2. 70
      caravel/insert_power.py
  3. 54
      caravel/process-microwatt-verilog.sh
  4. 36
      caravel_bram/DFFRAM.v
  5. 28
      caravel_bram/RAM_512x64.v
  6. 2
      common.vhdl
  7. 4
      core.vhdl
  8. 26
      dcache.vhdl
  9. 302
      dmi_dtm_jtag.vhdl
  10. 337
      even.hex
  11. 63
      fpga/main_bram_caravel.vhdl
  12. 232
      fpga/top-caravel.vhdl
  13. 39
      hello_world/head.S
  14. BIN
      hello_world/hello_world.bin
  15. BIN
      hello_world/hello_world.elf
  16. 462
      hello_world/hello_world.hex
  17. 4
      hello_world/powerpc.lds
  18. 2
      icache.vhdl
  19. 636
      jtag_tap/tap_top.v
  20. 53
      logic_analyzer.vhdl
  21. 929
      mc.vhdl
  22. 186
      mc_pkg.vhdl
  23. 30389
      microwatt.v
  24. 337
      odd.hex
  25. 24
      scripts/bin2hex-split.py
  26. 77
      soc.vhdl
  27. 2
      spi_flash_ctrl.vhdl
  28. 16
      spi_rxtx.vhdl
  29. 196
      verilator/jtag-verilator.c
  30. 17
      verilator/microwatt-verilator.cpp

23
Makefile

@ -52,7 +52,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \ @@ -52,7 +52,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \

soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
spi_rxtx.vhdl spi_flash_ctrl.vhdl
spi_rxtx.vhdl spi_flash_ctrl.vhdl logic_analyzer.vhdl

uart_files = $(wildcard uart16550/*.v)

@ -116,7 +116,7 @@ $(soc_dram_tbs): @@ -116,7 +116,7 @@ $(soc_dram_tbs):
else

VERILATOR_CFLAGS=-O3
VERILATOR_FLAGS=-O3
VERILATOR_FLAGS=-O3 --x-assign=1 --x-initial=1
verilated_dram: litedram/generated/sim/litedram_core.v
verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
@ -175,7 +175,7 @@ GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE @@ -175,7 +175,7 @@ GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE

clkgen=fpga/clk_gen_ecp5.vhd
toplevel=fpga/top-generic.vhdl
dmi_dtm=dmi_dtm_dummy.vhdl
dmi_dtm=dmi_dtm_jtag.vhdl dmi_dtm_dummy.vhdl

ifeq ($(FPGA_TARGET), verilator)
RESET_LOW=true
@ -184,9 +184,18 @@ CLK_FREQUENCY=50000000 @@ -184,9 +184,18 @@ CLK_FREQUENCY=50000000
clkgen=fpga/clk_gen_bypass.vhd
endif

ifeq ($(FPGA_TARGET), caravel)
RESET_LOW=true
CLK_INPUT=50000000
CLK_FREQUENCY=50000000
clkgen=fpga/clk_gen_bypass.vhd
toplevel=fpga/top-caravel.vhdl
MEMORY_SIZE=4096
endif

fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
nonrandom.vhdl
fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram_caravel.vhdl \
nonrandom.vhdl mc.vhdl mc_pkg.vhdl

synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)

@ -197,8 +206,8 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE) @@ -197,8 +206,8 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"

# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c verilator/jtag-verilator.c
verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c verilator/jtag-verilator.c -o $@ -Iuart16550 -Ijtag_tap -Icaravel_bram -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
make -C obj_dir -f Vmicrowatt.mk
@cp -f obj_dir/microwatt-verilator microwatt-verilator


70
caravel/insert_power.py

@ -0,0 +1,70 @@ @@ -0,0 +1,70 @@
#!/usr/bin/python

import sys
import re

module_regex = r'[a-zA-Z0-9_\.\\]+'

# match:
# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
module_re = re.compile(r'module\s+(' + module_regex + r')\((.*)\);')

# match:
# dcache_64_2_2_2_2_12_0 dcache_0 (
hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')

header1 = """\
`ifdef USE_POWER_PINS
vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2,
`endif\
"""

header2 = """\
`ifdef USE_POWER_PINS
inout vdda1; // User area 1 3.3V supply
inout vdda2; // User area 2 3.3V supply
inout vssa1; // User area 1 analog ground
inout vssa2; // User area 2 analog ground
inout vccd1; // User area 1 1.8V supply
inout vccd2; // User area 2 1.8v supply
inout vssd1; // User area 1 digital ground
inout vssd2; // User area 2 digital ground
`endif\
"""

header3 = """\
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
.vssa1(vssa1), // User area 1 analog ground
.vssa2(vssa2), // User area 2 analog ground
.vccd1(vccd1), // User area 1 1.8V power
.vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
`endif\
"""

if len(sys.argv) < 3:
print("Usage: insert_power.py verilog.v module1 module2..")
sys.exit(1);

verilog_file = sys.argv[1]
modules = sys.argv[2:]

with open(sys.argv[1]) as f:
for line in f:
m = module_re.match(line)
m2 = hookup_re.match(line)
if m and m.group(1) in modules:
module_name = m.group(1)
module_args = m.group(2)
print('module %s(' % module_name)
print(header1)
print(' %s);' % module_args)
print(header2)
elif m2 and m2.group(1) in modules:
print(line, end='')
print(header3)
else:
print(line, end='')

54
caravel/process-microwatt-verilog.sh

@ -0,0 +1,54 @@ @@ -0,0 +1,54 @@
#!/bin/bash -e

# process microwatt verilog

FILE=microwatt.v

# Remove these modules that are implemented as hard macros
for module in register_file_0_1489f923c4dca729178b3e3233458550d8dddf29 dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 plru_1 multiply_4
do
sed -i "/^module $module/,/^endmodule/d" $FILE
done

# Remove the debug bus in the places we call our macros
for module in dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0_1489f923c4dca729178b3e3233458550d8dddf29; do
for port in dbg_gpr log_out sim_dump; do
sed -i "/ $module /,/);/{ /$port/d }" $FILE
done
done

# Rename these modules to match the hard macro names
sed -i 's/register_file_0_1489f923c4dca729178b3e3233458550d8dddf29/register_file/' $FILE
sed -i 's/dcache_64_2_2_2_2_12_0/dcache/' $FILE
sed -i 's/icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f/icache/' $FILE
sed -i 's/toplevel/microwatt/' $FILE

# Add power to all macros, and route power in microwatt down to them
caravel/insert_power.py $FILE dcache icache register_file multiply_4 RAM_512x64 main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 microwatt core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a > $FILE.tmp && mv $FILE.tmp $FILE

# Add defines
sed -i '1 a\
\
/* Hard macros */\
`ifdef SIM\
`include "RAM_512x64.v"\
`include "register_file.v"\
`include "icache.v"\
`include "dcache.v"\
`include "multiply_4.v"\
`endif\
\
/* JTAG */\
`include "tap_top.v"\
\
/* UART */\
`include "raminfr.v"\
`include "uart_receiver.v"\
`include "uart_rfifo.v"\
`include "uart_tfifo.v"\
`include "uart_transmitter.v"\
`include "uart_defines.v"\
`include "uart_regs.v"\
`include "uart_sync_flops.v"\
`include "uart_wb.v"\
`include "uart_top.v"' $FILE

36
caravel_bram/DFFRAM.v

@ -0,0 +1,36 @@ @@ -0,0 +1,36 @@
module DFFRAM #( parameter COLS=1, filename="")
(
CLK,
WE,
EN,
Di,
Do,
A
);
localparam A_WIDTH = 8+$clog2(COLS);

input wire CLK;
input wire [3:0] WE;
input wire EN;
input wire [31:0] Di;
output reg [31:0] Do;
input wire [(A_WIDTH - 1): 0] A;

reg [31:0] RAM[(256*COLS)-1 : 0];
always @(posedge CLK)
if(EN) begin
Do <= RAM[A];
if(WE[0]) RAM[A][ 7: 0] <= Di[7:0];
if(WE[1]) RAM[A][15:8] <= Di[15:8];
if(WE[2]) RAM[A][23:16] <= Di[23:16];
if(WE[3]) RAM[A][31:24] <= Di[31:24];
end
else
Do <= 32'b0;
initial begin
$readmemh(filename, RAM);
end

endmodule

28
caravel_bram/RAM_512x64.v

@ -0,0 +1,28 @@ @@ -0,0 +1,28 @@
module RAM_512x64 (
input CLK,
input [7:0] WE,
input EN,
input [63:0] Di,
output [63:0] Do,
input [8:0] A
);
DFFRAM #(.COLS(2), .filename("even.hex")) LBANK (
.CLK(CLK),
.WE(WE[3:0]),
.EN(EN),
.Di(Di[31:0]),
.Do(Do[31:0]),
.A(A[8:0])
);

DFFRAM #(.COLS(2), .filename("odd.hex")) HBANK (
.CLK(CLK),
.WE(WE[7:4]),
.EN(EN),
.Di(Di[63:32]),
.Do(Do[63:32]),
.A(A[8:0])
);

endmodule

2
common.vhdl

@ -7,7 +7,7 @@ use work.decode_types.all; @@ -7,7 +7,7 @@ use work.decode_types.all;

package common is
-- Processor Version Number
constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630000";
constant PVR_MICROWATT : std_ulogic_vector(31 downto 0) := x"00630100";

-- MSR bit numbers
constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode

4
core.vhdl

@ -209,7 +209,7 @@ begin @@ -209,7 +209,7 @@ begin
generic map(
SIM => SIM,
LINE_SIZE => 64,
NUM_LINES => 64,
NUM_LINES => 2,
NUM_WAYS => 2,
LOG_LENGTH => LOG_LENGTH
)
@ -387,7 +387,7 @@ begin @@ -387,7 +387,7 @@ begin
dcache_0: entity work.dcache
generic map(
LINE_SIZE => 64,
NUM_LINES => 64,
NUM_LINES => 2,
NUM_WAYS => 2,
LOG_LENGTH => LOG_LENGTH
)

26
dcache.vhdl

@ -27,7 +27,7 @@ entity dcache is @@ -27,7 +27,7 @@ entity dcache is
-- Number of ways
NUM_WAYS : positive := 4;
-- L1 DTLB entries per set
TLB_SET_SIZE : positive := 64;
TLB_SET_SIZE : positive := 2;
-- L1 DTLB number of sets
TLB_NUM_WAYS : positive := 2;
-- L1 DTLB log_2(page_size)
@ -440,8 +440,12 @@ architecture rtl of dcache is @@ -440,8 +440,12 @@ architecture rtl of dcache is
function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t) return tlb_tag_t is
variable j : integer;
begin
if TLB_NUM_WAYS = 1 then
return tags;
else
j := way * TLB_EA_TAG_BITS;
return tags(j + TLB_EA_TAG_BITS - 1 downto j);
end if;
end;

-- Write a TLB tag to a TLB tag memory row
@ -449,23 +453,35 @@ architecture rtl of dcache is @@ -449,23 +453,35 @@ architecture rtl of dcache is
tag: tlb_tag_t) is
variable j : integer;
begin
if TLB_NUM_WAYS = 1 then
tags := tag;
else
j := way * TLB_EA_TAG_BITS;
tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
end if;
end;

-- Read a PTE from a TLB PTE memory row
function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t) return tlb_pte_t is
variable j : integer;
begin
if TLB_NUM_WAYS = 1 then
return ptes;
else
j := way * TLB_PTE_BITS;
return ptes(j + TLB_PTE_BITS - 1 downto j);
end if;
end;

procedure write_tlb_pte(way: tlb_way_t; ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
variable j : integer;
begin
if TLB_NUM_WAYS = 1 then
ptes := newpte;
else
j := way * TLB_PTE_BITS;
ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
end if;
end;

begin
@ -608,15 +624,15 @@ begin @@ -608,15 +624,15 @@ begin
hit := '1';
end if;
end loop;
tlb_hit <= hit and r0_valid;
tlb_hit <= hit and r0_valid and r0.req.virt_mode;
tlb_hit_way <= hitway;
if tlb_hit = '1' then
pte <= read_tlb_pte(hitway, tlb_pte_way);
else
pte <= (others => '0');
end if;
valid_ra <= tlb_hit or not r0.req.virt_mode;
if r0.req.virt_mode = '1' then
valid_ra <= tlb_hit or (r0_valid and not r0.req.virt_mode);
if tlb_hit = '1' then
ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
(ROW_OFF_BITS-1 downto 0 => '0');
@ -831,7 +847,7 @@ begin @@ -831,7 +847,7 @@ begin
-- work out whether we have permission for this access
-- NB we don't yet implement AMR, thus no KUAP
rc_ok <= perm_attr.reference and (r0.req.load or perm_attr.changed);
perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
perm_ok <= ((r0.req.priv_mode and r0.req.valid) or not perm_attr.priv) and
(perm_attr.wr_perm or (r0.req.load and perm_attr.rd_perm));
access_ok <= valid_ra and perm_ok and rc_ok;


302
dmi_dtm_jtag.vhdl

@ -0,0 +1,302 @@ @@ -0,0 +1,302 @@
-- JTAG to DMI interface, based on the Xilinx version
--
-- DMI bus
--
-- req : ____/------------\_____
-- addr: xxxx< >xxxxx, based on the Xilinx version
-- dout: xxxx< >xxxxx
-- wr : xxxx< >xxxxx
-- din : xxxxxxxxxxxx< >xxx
-- ack : ____________/------\___
--
-- * addr/dout set along with req, can be latched on same cycle by slave
-- * ack & din remain up until req is dropped by master, the slave must
-- provide a stable output on din on reads during that time.
-- * req remains low at until at least one sysclk after ack seen down.
--
-- JTAG (tck) DMI (sys_clk)
--
-- * jtag_req = 1
-- (jtag_req_0) *
-- (jtag_req_1) -> * dmi_req = 1 >
-- *.../...
-- * dmi_ack = 1 <
-- * (dmi_ack_0)
-- * <- (dmi_ack_1)
-- * jtag_req = 0 (and latch dmi_din)
-- (jtag_req_0) *
-- (jtag_req_1) -> * dmi_req = 0 >
-- * dmi_ack = 0 <
-- * (dmi_ack_0)
-- * <- (dmi_ack_1)
--
-- jtag_req can go back to 1 when jtag_rsp_1 is 0
--
-- Questions/TODO:
-- - I use 2 flip fops for sync, is that enough ?
-- - I treat the jtag_trst as an async reset, is that necessary ?
-- - Dbl check reset situation since we have two different resets
-- each only resetting part of the logic...
-- - Look at optionally removing the synchronizer on the ack path,
-- assuming JTAG is always slow enough that ack will have been
-- stable long enough by the time CAPTURE comes in.
-- - We could avoid the latched request by not shifting while a
-- request is in progress (and force TDO to 1 to return a busy
-- status).
--
-- WARNING: This isn't the real DMI JTAG protocol (at least not yet).
-- a command while busy will be ignored. A response of "11"
-- means the previous command is still going, try again.
-- As such We don't implement the DMI "error" status, and
-- we don't implement DTMCS yet... This may still all change
-- but for now it's easier that way as the real DMI protocol
-- requires for a command to work properly that enough TCK
-- are sent while IDLE and I'm having trouble getting that
-- working with UrJtag and the Xilinx BSCAN2 for now.

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

library work;
use work.wishbone_types.all;

entity dmi_dtm_jtag is
generic(ABITS : INTEGER:=8;
DBITS : INTEGER:=32);

port(sys_clk : in std_ulogic;
sys_reset : in std_ulogic;
dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
dmi_req : out std_ulogic;
dmi_wr : out std_ulogic;
dmi_ack : in std_ulogic;
-- dmi_err : in std_ulogic TODO: Add error response
jtag_tck : in std_ulogic;
jtag_tdi : in std_ulogic;
jtag_tms : in std_ulogic;
jtag_trst : in std_ulogic;
jtag_tdo : out std_ulogic
);
end entity dmi_dtm_jtag;

architecture behaviour of dmi_dtm_jtag is

-- Signals coming out of the JTAG TAP controller
signal capture : std_ulogic;
signal update : std_ulogic;
signal sel : std_ulogic;
signal shift : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;

-- ** JTAG clock domain **

-- Shift register
signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);

-- Latched request
signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);

-- A request is present
signal jtag_req : std_ulogic;

-- Synchronizer for jtag_rsp (sys clk -> jtag_tck)
signal dmi_ack_0 : std_ulogic;
signal dmi_ack_1 : std_ulogic;

-- ** sys clock domain **

-- Synchronizer for jtag_req (jtag clk -> sys clk)
signal jtag_req_0 : std_ulogic;
signal jtag_req_1 : std_ulogic;

-- ** combination signals
signal jtag_bsy : std_ulogic;
signal op_valid : std_ulogic;
signal rsp_op : std_ulogic_vector(1 downto 0);

-- ** Constants **
constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";

attribute ASYNC_REG : string;
attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";

component tap_top port (
-- JTAG pads
tms_pad_i : in std_ulogic;
tck_pad_i : in std_ulogic;
trst_pad_i : in std_ulogic;
tdi_pad_i : in std_ulogic;
tdo_pad_o : out std_ulogic;
tdo_padoe_o : out std_ulogic;

-- TAP states
shift_dr_o : out std_ulogic;
pause_dr_o : out std_ulogic;
update_dr_o : out std_ulogic;
capture_dr_o : out std_ulogic;

-- Select signals for boundary scan or mbist
extest_select_o : out std_ulogic;
sample_preload_select_o : out std_ulogic;
mbist_select_o : out std_ulogic;
debug_select_o : out std_ulogic;

-- TDO signal that is connected to TDI of sub-modules.
tdo_o : out std_ulogic;

-- TDI signals from sub-modules
debug_tdi_i : in std_ulogic;
bs_chain_tdi_i : in std_ulogic;
mbist_tdi_i : in std_ulogic
);
end component;

begin
tap_top0 : tap_top
port map (
tms_pad_i => jtag_tms,
tck_pad_i => jtag_tck,
trst_pad_i => jtag_trst,
tdi_pad_i => jtag_tdi,
tdo_pad_o => jtag_tdo,
tdo_padoe_o => open, -- what to do with this?

shift_dr_o => shift,
pause_dr_o => open, -- what to do with this?
update_dr_o => update,
capture_dr_o => capture,

-- connect boundary scan and mbist?
extest_select_o => open,
sample_preload_select_o => open,
mbist_select_o => open,
debug_select_o => sel,

tdo_o => tdi,
debug_tdi_i => tdo,
bs_chain_tdi_i => '0',
mbist_tdi_i => '0'
);

-- dmi_req synchronization
dmi_req_sync : process(sys_clk)
begin
-- sys_reset is synchronous
if rising_edge(sys_clk) then
if (sys_reset = '1') then
jtag_req_0 <= '0';
jtag_req_1 <= '0';
else
jtag_req_0 <= jtag_req;
jtag_req_1 <= jtag_req_0;
end if;
end if;
end process;
dmi_req <= jtag_req_1;

-- dmi_ack synchronization
dmi_ack_sync: process(jtag_tck, jtag_trst)
begin
-- jtag_trst is async (see comments)
if jtag_trst = '1' then
dmi_ack_0 <= '0';
dmi_ack_1 <= '0';
elsif rising_edge(jtag_tck) then
dmi_ack_0 <= dmi_ack;
dmi_ack_1 <= dmi_ack_0;
end if;
end process;

-- jtag_bsy indicates whether we can start a new request, we can when
-- we aren't already processing one (jtag_req) and the synchronized ack
-- of the previous one is 0.
--
jtag_bsy <= jtag_req or dmi_ack_1;

-- decode request type in shift register
with shiftr(1 downto 0) select op_valid <=
'1' when DMI_REQ_RD,
'1' when DMI_REQ_WR,
'0' when others;

-- encode response op
rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;

-- Some DMI out signals are directly driven from the request register
dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
dmi_dout <= request(DBITS + 1 downto 2);
dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';

-- TDO is wired to shift register bit 0
tdo <= shiftr(0);

-- Main state machine. Handles shift registers, request latch and
-- jtag_req latch. Could be split into 3 processes but it's probably
-- not worthwhile.
--
shifter: process(jtag_tck, jtag_trst, sys_reset)
begin
if jtag_trst = '1' or sys_reset = '1' then
shiftr <= (others => '0');
jtag_req <= '0';
request <= (others => '0');
elsif rising_edge(jtag_tck) then

-- Handle jtag "commands" when sel is 1
if sel = '1' then
-- Shift state, rotate the register
if shift = '1' then
shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
end if;

-- Update state (trigger)
--
-- Latch the request if we aren't already processing one and
-- it has a valid command opcode.
--
if update = '1' and op_valid = '1' then
if jtag_bsy = '0' then
request <= shiftr;
jtag_req <= '1';
end if;
-- Set the shift register "op" to "busy". This will prevent
-- us from re-starting the command on the next update if
-- the command completes before that.
shiftr(1 downto 0) <= DMI_RSP_BSY;
end if;

-- Request completion.
--
-- Capture the response data for reads and clear request flag.
--
-- Note: We clear req (and thus dmi_req) here which relies on tck
-- ticking and sel set. This means we are stuck with dmi_req up if
-- the jtag interface stops. Slaves must be resilient to this.
--
if jtag_req = '1' and dmi_ack_1 = '1' then
jtag_req <= '0';
if request(1 downto 0) = DMI_REQ_RD then
request(DBITS + 1 downto 2) <= dmi_din;
end if;
end if;

-- Capture state, grab latch content with updated status
if capture = '1' then
shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
end if;

end if;
end if;
end process;
end architecture behaviour;

337
even.hex

@ -0,0 +1,337 @@ @@ -0,0 +1,337 @@
4800012c
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63
fpga/main_bram_caravel.vhdl

@ -0,0 +1,63 @@ @@ -0,0 +1,63 @@
library ieee;
use ieee.std_logic_1164.all;

library work;

entity main_bram is
generic(
WIDTH : natural := 64;
HEIGHT_BITS : natural := 11;
MEMORY_SIZE : natural := (8*1024);
RAM_INIT_FILE : string
);
port(
clk : in std_logic;
addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
di : in std_logic_vector(WIDTH-1 downto 0);
do : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector((WIDTH/8)-1 downto 0);
re : in std_ulogic;
we : in std_ulogic
);
end entity main_bram;

architecture behaviour of main_bram is
component RAM_512x64 port (
CLK : in std_ulogic;
WE : in std_ulogic_vector(7 downto 0);
EN : in std_ulogic;
Di : in std_ulogic_vector(63 downto 0);
Do : out std_ulogic_vector(63 downto 0);
A : in std_ulogic_vector(8 downto 0)
);
end component;

signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);

signal obuf : std_logic_vector(WIDTH-1 downto 0);
begin
assert WIDTH = 64;
-- Do we have a log2 round up issue here?
assert HEIGHT_BITS = 10;
assert MEMORY_SIZE = (4*1024);

sel_qual <= sel when we = '1' else (others => '0');

memory_0 : RAM_512x64
port map (
CLK => clk,
WE => sel_qual(7 downto 0),
EN => re or we,
Di => di(63 downto 0),
Do => obuf(63 downto 0),
A => addr(8 downto 0)
);

-- The wishbone BRAM wrapper assumes a 1 cycle delay
memory_read_buffer: process(clk)
begin
if rising_edge(clk) then
do <= obuf;
end if;
end process;
end architecture behaviour;

232
fpga/top-caravel.vhdl

@ -0,0 +1,232 @@ @@ -0,0 +1,232 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.wishbone_types.all;

entity toplevel is
generic (
MEMORY_SIZE : integer := 8192;
RAM_INIT_FILE : string := "firmware.hex";
RESET_LOW : boolean := true;
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
HAS_FPU : boolean := false;
NO_BRAM : boolean := false;
DISABLE_FLATTEN_CORE : boolean := false;
SPI_FLASH_OFFSET : integer := 0;
SPI_FLASH_DEF_CKDV : natural := 4;
SPI_FLASH_DEF_QUAD : boolean := false;
LOG_LENGTH : natural := 0;
UART_IS_16550 : boolean := true;
HAS_UART1 : boolean := false;
HAS_JTAG : boolean := true;
INPUT_IOS : integer range 0 to 32 := 32;
OUTPUT_IOS : integer range 0 to 32 := 32
);
port(
ext_clk : in std_ulogic;
ext_rst : in std_ulogic;

-- UART0 signals:
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;

-- UART1 signals:
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;

-- SPI
spi_flash_cs_n : out std_ulogic;
spi_flash_clk : out std_ulogic;
spi_flash_sdat_i : in std_ulogic_vector(3 downto 0);
spi_flash_sdat_o : out std_ulogic_vector(3 downto 0);
spi_flash_sdat_oe : out std_ulogic_vector(3 downto 0);

-- JTAG signals:
jtag_tck : in std_ulogic;
jtag_tdi : in std_ulogic;
jtag_tms : in std_ulogic;
jtag_trst : in std_ulogic;
jtag_tdo : out std_ulogic;

-- Bill's bus
oib_clk : out std_ulogic;
ob_data : out std_ulogic_vector(7 downto 0);
ob_pty : out std_ulogic;

ib_data : in std_ulogic_vector(7 downto 0);
ib_pty : in std_ulogic;

-- IO Signals
gpio_out : out std_ulogic_vector(OUTPUT_IOS-1 downto 0);
gpio_in : in std_ulogic_vector(INPUT_IOS-1 downto 0);

-- Add an I/O pin to select fetching from flash on reset
alt_reset : in std_ulogic
);
end entity toplevel;

architecture behaviour of toplevel is
-- reset signals
signal system_rst : std_ulogic;

-- external bus wishbone connection
signal wb_dram_out : wishbone_master_out;
signal wb_dram_in : wishbone_slave_out;

-- external bus
signal wb_mc_adr : wishbone_addr_type;
signal wb_mc_dat_o : wishbone_data_type;
signal wb_mc_cyc : std_ulogic;
signal wb_mc_stb : std_ulogic;
signal wb_mc_sel : wishbone_sel_type;
signal wb_mc_we : std_ulogic;
signal wb_mc_dat_i : wishbone_data_type;
signal wb_mc_ack : std_ulogic;
signal wb_mc_stall : std_ulogic;

signal wb_logic_analyzer_out : wb_io_slave_out := wb_io_slave_out_init;
signal wb_logic_analyzer_in : wb_io_master_out;

signal wb_ext_io_in : wb_io_master_out;
signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_eth : std_ulogic;

begin

system_rst <= not ext_rst when RESET_LOW else ext_rst;

-- Main SoC
soc0: entity work.soc
generic map(
MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => RAM_INIT_FILE,
SIM => false,
CLK_FREQ => CLK_FREQUENCY,
HAS_FPU => HAS_FPU,
HAS_DRAM => true,
DRAM_SIZE => 0,
DRAM_INIT_SIZE => 0,
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
LOG_LENGTH => LOG_LENGTH,
UART0_IS_16550 => UART_IS_16550,
HAS_UART1 => HAS_UART1,
HAS_JTAG => HAS_JTAG,
HAS_LITEETH => true
)
port map (
-- System signals
system_clk => ext_clk,
rst => system_rst,

-- UART signals
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,

-- UART1 signals
uart1_txd => uart1_txd,
uart1_rxd => uart1_rxd,

-- SPI signals
spi_flash_sck => spi_flash_clk,
spi_flash_cs_n => spi_flash_cs_n,
spi_flash_sdat_o => spi_flash_sdat_o,
spi_flash_sdat_oe => spi_flash_sdat_oe,
spi_flash_sdat_i => spi_flash_sdat_i,

-- JTAG signals
jtag_tck => jtag_tck,
jtag_tdi => jtag_tdi,
jtag_tms => jtag_tms,
jtag_trst => jtag_trst,
jtag_tdo => jtag_tdo,

-- Use DRAM wishbone for Bill's bus
wb_dram_in => wb_dram_out,
wb_dram_out => wb_dram_in,

wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out,
wb_ext_is_eth => wb_ext_is_eth,

-- Reset PC to flash offset 0 (ie 0xf000000)
alt_reset => alt_reset
);

mc0: entity work.mc
generic map(
WB_AW => 32, -- wishbone_addr_bits
WB_DW => 64, -- wishbone_data_bits
OIB_DW => 8,
OIB_RATIO => 2, -- bill said this
BAR_INIT => x"1fff" -- dram has 512 bit space. CPU gives
-- top 3 bits as 0. carve off small
-- chunk at top for config space.
)
port map (
clk => ext_clk,
rst => system_rst,

wb_cyc => wb_mc_cyc,
wb_stb => wb_mc_stb,
wb_we => wb_mc_we,
wb_addr => wb_mc_adr,
wb_wr_data => wb_mc_dat_o,
wb_sel => wb_mc_sel,
wb_ack => wb_mc_ack,
-- wb_err => wb_mc_err, ??
wb_stall => wb_mc_stall,
wb_rd_data => wb_mc_dat_i,
oib_clk => oib_clk,
ob_data => ob_data,
ob_pty => ob_pty,
ib_data => ib_data,
ib_pty => ib_pty
-- err => ob _err,
-- int => ob int
);

logic_analyzer: entity work.logic_analyzer
generic map(
INPUT_IOS => INPUT_IOS,
OUTPUT_IOS => OUTPUT_IOS
)
port map(
clk => ext_clk,
rst => system_rst,
wb_in => wb_logic_analyzer_in,
wb_out => wb_logic_analyzer_out,
io_in => gpio_in,
io_out => gpio_out
);

wb_logic_analyzer_in.adr <= wb_ext_io_in.adr;
wb_logic_analyzer_in.dat <= wb_ext_io_in.dat;
wb_logic_analyzer_in.cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
wb_logic_analyzer_in.stb <= wb_ext_io_in.stb;
wb_logic_analyzer_in.sel <= wb_ext_io_in.sel;
wb_logic_analyzer_in.we <= wb_ext_io_in.we;

wb_ext_io_out <= wb_logic_analyzer_out;


-- External bus wishbone
wb_mc_adr <= wb_dram_out.adr;
wb_mc_dat_o <= wb_dram_out.dat;
wb_mc_cyc <= wb_dram_out.cyc;
wb_mc_stb <= wb_dram_out.stb;
wb_mc_sel <= wb_dram_out.sel;
wb_mc_we <= wb_dram_out.we;

wb_dram_in.dat <= wb_mc_dat_i;
wb_dram_in.ack <= wb_mc_ack;
wb_dram_in.stall <= wb_mc_stall;

end architecture behaviour;

39
hello_world/head.S

@ -66,42 +66,3 @@ boot_entry: @@ -66,42 +66,3 @@ boot_entry:
mtctr %r12,
bctrl
b .

#define EXCEPTION(nr) \
.= nr ;\
b .

/* More exception stubs */
EXCEPTION(0x300)
EXCEPTION(0x380)
EXCEPTION(0x400)
EXCEPTION(0x480)
EXCEPTION(0x500)
EXCEPTION(0x600)
EXCEPTION(0x700)
EXCEPTION(0x800)
EXCEPTION(0x900)
EXCEPTION(0x980)
EXCEPTION(0xa00)
EXCEPTION(0xb00)
EXCEPTION(0xc00)
EXCEPTION(0xd00)
EXCEPTION(0xe00)
EXCEPTION(0xe20)
EXCEPTION(0xe40)
EXCEPTION(0xe60)
EXCEPTION(0xe80)
EXCEPTION(0xf00)
EXCEPTION(0xf20)
EXCEPTION(0xf40)
EXCEPTION(0xf60)
EXCEPTION(0xf80)
#if 0
EXCEPTION(0x1000)
EXCEPTION(0x1100)
EXCEPTION(0x1200)
EXCEPTION(0x1300)
EXCEPTION(0x1400)
EXCEPTION(0x1500)
EXCEPTION(0x1600)
#endif

BIN
hello_world/hello_world.bin

Binary file not shown.

BIN
hello_world/hello_world.elf

Binary file not shown.

462
hello_world/hello_world.hex

@ -40,7 +40,7 @@ a64b5a7d14004a39 @@ -40,7 +40,7 @@ a64b5a7d14004a39
60211f0064210000
618c00003d800000
658c0000798c07c6
7d8903a6618c1014
7d8903a6618c0414
480000004e800421
0000000000000000
0000000000000000
@ -94,7 +94,6 @@ a64b5a7d14004a39 @@ -94,7 +94,6 @@ a64b5a7d14004a39
0000000000000000
0000000000000000
0000000000000000
0000000048000000
0000000000000000
0000000000000000
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@ -110,7 +109,6 @@ a64b5a7d14004a39 @@ -110,7 +109,6 @@ a64b5a7d14004a39
0000000000000000
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@ -126,394 +124,12 @@ a64b5a7d14004a39 @@ -126,394 +124,12 @@ a64b5a7d14004a39
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