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caravel-20
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30 changed files with 34008 additions and 538 deletions
@ -0,0 +1,70 @@
@@ -0,0 +1,70 @@
|
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#!/usr/bin/python |
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|
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import sys |
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import re |
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|
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module_regex = r'[a-zA-Z0-9_\.\\]+' |
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|
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# match: |
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# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out); |
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module_re = re.compile(r'module\s+(' + module_regex + r')\((.*)\);') |
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|
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# match: |
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# dcache_64_2_2_2_2_12_0 dcache_0 ( |
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hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(') |
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|
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header1 = """\ |
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`ifdef USE_POWER_PINS |
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vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2, |
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`endif\ |
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""" |
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|
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header2 = """\ |
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`ifdef USE_POWER_PINS |
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inout vdda1; // User area 1 3.3V supply |
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inout vdda2; // User area 2 3.3V supply |
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inout vssa1; // User area 1 analog ground |
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inout vssa2; // User area 2 analog ground |
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inout vccd1; // User area 1 1.8V supply |
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inout vccd2; // User area 2 1.8v supply |
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inout vssd1; // User area 1 digital ground |
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inout vssd2; // User area 2 digital ground |
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`endif\ |
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""" |
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|
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header3 = """\ |
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`ifdef USE_POWER_PINS |
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.vdda1(vdda1), // User area 1 3.3V power |
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.vdda2(vdda2), // User area 2 3.3V power |
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.vssa1(vssa1), // User area 1 analog ground |
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.vssa2(vssa2), // User area 2 analog ground |
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.vccd1(vccd1), // User area 1 1.8V power |
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.vccd2(vccd2), // User area 2 1.8V power |
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.vssd1(vssd1), // User area 1 digital ground |
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.vssd2(vssd2), // User area 2 digital ground |
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`endif\ |
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""" |
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|
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if len(sys.argv) < 3: |
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print("Usage: insert_power.py verilog.v module1 module2..") |
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sys.exit(1); |
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|
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verilog_file = sys.argv[1] |
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modules = sys.argv[2:] |
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|
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with open(sys.argv[1]) as f: |
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for line in f: |
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m = module_re.match(line) |
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m2 = hookup_re.match(line) |
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if m and m.group(1) in modules: |
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module_name = m.group(1) |
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module_args = m.group(2) |
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print('module %s(' % module_name) |
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print(header1) |
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print(' %s);' % module_args) |
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print(header2) |
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elif m2 and m2.group(1) in modules: |
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print(line, end='') |
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print(header3) |
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else: |
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print(line, end='') |
@ -0,0 +1,54 @@
@@ -0,0 +1,54 @@
|
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#!/bin/bash -e |
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|
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# process microwatt verilog |
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FILE=microwatt.v |
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|
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# Remove these modules that are implemented as hard macros |
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for module in register_file_0_1489f923c4dca729178b3e3233458550d8dddf29 dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 plru_1 multiply_4 |
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do |
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sed -i "/^module $module/,/^endmodule/d" $FILE |
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done |
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|
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# Remove the debug bus in the places we call our macros |
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for module in dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0_1489f923c4dca729178b3e3233458550d8dddf29; do |
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for port in dbg_gpr log_out sim_dump; do |
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sed -i "/ $module /,/);/{ /$port/d }" $FILE |
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done |
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done |
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|
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# Rename these modules to match the hard macro names |
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sed -i 's/register_file_0_1489f923c4dca729178b3e3233458550d8dddf29/register_file/' $FILE |
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sed -i 's/dcache_64_2_2_2_2_12_0/dcache/' $FILE |
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sed -i 's/icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f/icache/' $FILE |
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sed -i 's/toplevel/microwatt/' $FILE |
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|
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# Add power to all macros, and route power in microwatt down to them |
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caravel/insert_power.py $FILE dcache icache register_file multiply_4 RAM_512x64 main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 microwatt core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a > $FILE.tmp && mv $FILE.tmp $FILE |
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|
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# Add defines |
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sed -i '1 a\ |
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\ |
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/* Hard macros */\ |
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`ifdef SIM\ |
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`include "RAM_512x64.v"\ |
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`include "register_file.v"\ |
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`include "icache.v"\ |
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`include "dcache.v"\ |
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`include "multiply_4.v"\ |
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`endif\ |
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\ |
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/* JTAG */\ |
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`include "tap_top.v"\ |
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\ |
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/* UART */\ |
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`include "raminfr.v"\ |
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`include "uart_receiver.v"\ |
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`include "uart_rfifo.v"\ |
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`include "uart_tfifo.v"\ |
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`include "uart_transmitter.v"\ |
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`include "uart_defines.v"\ |
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`include "uart_regs.v"\ |
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`include "uart_sync_flops.v"\ |
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`include "uart_wb.v"\ |
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`include "uart_top.v"' $FILE |
@ -0,0 +1,36 @@
@@ -0,0 +1,36 @@
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module DFFRAM #( parameter COLS=1, filename="") |
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( |
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CLK, |
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WE, |
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EN, |
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Di, |
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Do, |
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A |
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); |
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localparam A_WIDTH = 8+$clog2(COLS); |
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|
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input wire CLK; |
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input wire [3:0] WE; |
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input wire EN; |
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input wire [31:0] Di; |
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output reg [31:0] Do; |
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input wire [(A_WIDTH - 1): 0] A; |
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reg [31:0] RAM[(256*COLS)-1 : 0]; |
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always @(posedge CLK) |
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if(EN) begin |
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Do <= RAM[A]; |
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if(WE[0]) RAM[A][ 7: 0] <= Di[7:0]; |
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if(WE[1]) RAM[A][15:8] <= Di[15:8]; |
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if(WE[2]) RAM[A][23:16] <= Di[23:16]; |
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if(WE[3]) RAM[A][31:24] <= Di[31:24]; |
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end |
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else |
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Do <= 32'b0; |
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initial begin |
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$readmemh(filename, RAM); |
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end |
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endmodule |
@ -0,0 +1,28 @@
@@ -0,0 +1,28 @@
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module RAM_512x64 ( |
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input CLK, |
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input [7:0] WE, |
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input EN, |
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input [63:0] Di, |
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output [63:0] Do, |
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input [8:0] A |
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); |
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|
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DFFRAM #(.COLS(2), .filename("even.hex")) LBANK ( |
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.CLK(CLK), |
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.WE(WE[3:0]), |
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.EN(EN), |
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.Di(Di[31:0]), |
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.Do(Do[31:0]), |
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.A(A[8:0]) |
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); |
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|
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DFFRAM #(.COLS(2), .filename("odd.hex")) HBANK ( |
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.CLK(CLK), |
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.WE(WE[7:4]), |
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.EN(EN), |
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.Di(Di[63:32]), |
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.Do(Do[63:32]), |
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.A(A[8:0]) |
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); |
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|
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endmodule |
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@@ -0,0 +1,302 @@
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-- JTAG to DMI interface, based on the Xilinx version |
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-- |
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-- DMI bus |
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-- |
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-- req : ____/------------\_____ |
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-- addr: xxxx< >xxxxx, based on the Xilinx version |
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-- dout: xxxx< >xxxxx |
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-- wr : xxxx< >xxxxx |
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-- din : xxxxxxxxxxxx< >xxx |
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-- ack : ____________/------\___ |
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-- |
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-- * addr/dout set along with req, can be latched on same cycle by slave |
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-- * ack & din remain up until req is dropped by master, the slave must |
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-- provide a stable output on din on reads during that time. |
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-- * req remains low at until at least one sysclk after ack seen down. |
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-- |
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-- JTAG (tck) DMI (sys_clk) |
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-- |
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-- * jtag_req = 1 |
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-- (jtag_req_0) * |
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-- (jtag_req_1) -> * dmi_req = 1 > |
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-- *.../... |
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-- * dmi_ack = 1 < |
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-- * (dmi_ack_0) |
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-- * <- (dmi_ack_1) |
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-- * jtag_req = 0 (and latch dmi_din) |
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-- (jtag_req_0) * |
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-- (jtag_req_1) -> * dmi_req = 0 > |
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-- * dmi_ack = 0 < |
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-- * (dmi_ack_0) |
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-- * <- (dmi_ack_1) |
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-- |
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-- jtag_req can go back to 1 when jtag_rsp_1 is 0 |
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-- |
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-- Questions/TODO: |
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-- - I use 2 flip fops for sync, is that enough ? |
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-- - I treat the jtag_trst as an async reset, is that necessary ? |
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-- - Dbl check reset situation since we have two different resets |
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-- each only resetting part of the logic... |
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-- - Look at optionally removing the synchronizer on the ack path, |
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-- assuming JTAG is always slow enough that ack will have been |
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-- stable long enough by the time CAPTURE comes in. |
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-- - We could avoid the latched request by not shifting while a |
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-- request is in progress (and force TDO to 1 to return a busy |
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-- status). |
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-- |
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-- WARNING: This isn't the real DMI JTAG protocol (at least not yet). |
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-- a command while busy will be ignored. A response of "11" |
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-- means the previous command is still going, try again. |
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-- As such We don't implement the DMI "error" status, and |
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-- we don't implement DTMCS yet... This may still all change |
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-- but for now it's easier that way as the real DMI protocol |
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-- requires for a command to work properly that enough TCK |
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-- are sent while IDLE and I'm having trouble getting that |
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-- working with UrJtag and the Xilinx BSCAN2 for now. |
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|
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.math_real.all; |
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|
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library work; |
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use work.wishbone_types.all; |
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|
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entity dmi_dtm_jtag is |
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generic(ABITS : INTEGER:=8; |
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DBITS : INTEGER:=32); |
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|
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port(sys_clk : in std_ulogic; |
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sys_reset : in std_ulogic; |
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0); |
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0); |
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0); |
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dmi_req : out std_ulogic; |
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dmi_wr : out std_ulogic; |
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dmi_ack : in std_ulogic; |
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-- dmi_err : in std_ulogic TODO: Add error response |
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jtag_tck : in std_ulogic; |
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jtag_tdi : in std_ulogic; |
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jtag_tms : in std_ulogic; |
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jtag_trst : in std_ulogic; |
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jtag_tdo : out std_ulogic |
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); |
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end entity dmi_dtm_jtag; |
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|
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architecture behaviour of dmi_dtm_jtag is |
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|
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-- Signals coming out of the JTAG TAP controller |
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signal capture : std_ulogic; |
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signal update : std_ulogic; |
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signal sel : std_ulogic; |
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signal shift : std_ulogic; |
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signal tdi : std_ulogic; |
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signal tdo : std_ulogic; |
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|
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-- ** JTAG clock domain ** |
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|
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-- Shift register |
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signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0); |
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|
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-- Latched request |
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signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0); |
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|
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-- A request is present |
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signal jtag_req : std_ulogic; |
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|
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-- Synchronizer for jtag_rsp (sys clk -> jtag_tck) |
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signal dmi_ack_0 : std_ulogic; |
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signal dmi_ack_1 : std_ulogic; |
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|
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-- ** sys clock domain ** |
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|
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-- Synchronizer for jtag_req (jtag clk -> sys clk) |
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signal jtag_req_0 : std_ulogic; |
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signal jtag_req_1 : std_ulogic; |
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|
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-- ** combination signals |
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signal jtag_bsy : std_ulogic; |
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signal op_valid : std_ulogic; |
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signal rsp_op : std_ulogic_vector(1 downto 0); |
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|
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-- ** Constants ** |
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constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00"; |
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constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01"; |
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constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10"; |
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constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00"; |
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constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11"; |
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|
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attribute ASYNC_REG : string; |
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attribute ASYNC_REG of jtag_req_0: signal is "TRUE"; |
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attribute ASYNC_REG of jtag_req_1: signal is "TRUE"; |
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attribute ASYNC_REG of dmi_ack_0: signal is "TRUE"; |
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attribute ASYNC_REG of dmi_ack_1: signal is "TRUE"; |
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|
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component tap_top port ( |
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-- JTAG pads |
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tms_pad_i : in std_ulogic; |
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tck_pad_i : in std_ulogic; |
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trst_pad_i : in std_ulogic; |
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tdi_pad_i : in std_ulogic; |
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tdo_pad_o : out std_ulogic; |
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tdo_padoe_o : out std_ulogic; |
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|
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-- TAP states |
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shift_dr_o : out std_ulogic; |
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pause_dr_o : out std_ulogic; |
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update_dr_o : out std_ulogic; |
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capture_dr_o : out std_ulogic; |
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|
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-- Select signals for boundary scan or mbist |
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extest_select_o : out std_ulogic; |
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sample_preload_select_o : out std_ulogic; |
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mbist_select_o : out std_ulogic; |
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debug_select_o : out std_ulogic; |
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|
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-- TDO signal that is connected to TDI of sub-modules. |
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tdo_o : out std_ulogic; |
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|
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-- TDI signals from sub-modules |
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debug_tdi_i : in std_ulogic; |
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bs_chain_tdi_i : in std_ulogic; |
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mbist_tdi_i : in std_ulogic |
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); |
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end component; |
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|
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begin |
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tap_top0 : tap_top |
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port map ( |
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tms_pad_i => jtag_tms, |
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tck_pad_i => jtag_tck, |
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trst_pad_i => jtag_trst, |
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tdi_pad_i => jtag_tdi, |
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tdo_pad_o => jtag_tdo, |
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tdo_padoe_o => open, -- what to do with this? |
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|
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shift_dr_o => shift, |
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pause_dr_o => open, -- what to do with this? |
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update_dr_o => update, |
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capture_dr_o => capture, |
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|
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-- connect boundary scan and mbist? |
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extest_select_o => open, |
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sample_preload_select_o => open, |
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mbist_select_o => open, |
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debug_select_o => sel, |
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|
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tdo_o => tdi, |
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debug_tdi_i => tdo, |
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bs_chain_tdi_i => '0', |
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mbist_tdi_i => '0' |
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); |
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|
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-- dmi_req synchronization |
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dmi_req_sync : process(sys_clk) |
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begin |
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-- sys_reset is synchronous |
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if rising_edge(sys_clk) then |
||||
if (sys_reset = '1') then |
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jtag_req_0 <= '0'; |
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jtag_req_1 <= '0'; |
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else |
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jtag_req_0 <= jtag_req; |
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jtag_req_1 <= jtag_req_0; |
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end if; |
||||
end if; |
||||
end process; |
||||
dmi_req <= jtag_req_1; |
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|
||||
-- dmi_ack synchronization |
||||
dmi_ack_sync: process(jtag_tck, jtag_trst) |
||||
begin |
||||
-- jtag_trst is async (see comments) |
||||
if jtag_trst = '1' then |
||||
dmi_ack_0 <= '0'; |
||||
dmi_ack_1 <= '0'; |
||||
elsif rising_edge(jtag_tck) then |
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dmi_ack_0 <= dmi_ack; |
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dmi_ack_1 <= dmi_ack_0; |
||||
end if; |
||||
end process; |
||||
|
||||
-- jtag_bsy indicates whether we can start a new request, we can when |
||||
-- we aren't already processing one (jtag_req) and the synchronized ack |
||||
-- of the previous one is 0. |
||||
-- |
||||
jtag_bsy <= jtag_req or dmi_ack_1; |
||||
|
||||
-- decode request type in shift register |
||||
with shiftr(1 downto 0) select op_valid <= |
||||
'1' when DMI_REQ_RD, |
||||
'1' when DMI_REQ_WR, |
||||
'0' when others; |
||||
|
||||
-- encode response op |
||||
rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK; |
||||
|
||||
-- Some DMI out signals are directly driven from the request register |
||||
dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2); |
||||
dmi_dout <= request(DBITS + 1 downto 2); |
||||
dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0'; |
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|
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-- TDO is wired to shift register bit 0 |
||||
tdo <= shiftr(0); |
||||
|
||||
-- Main state machine. Handles shift registers, request latch and |
||||
-- jtag_req latch. Could be split into 3 processes but it's probably |
||||
-- not worthwhile. |
||||
-- |
||||
shifter: process(jtag_tck, jtag_trst, sys_reset) |
||||
begin |
||||
if jtag_trst = '1' or sys_reset = '1' then |
||||
shiftr <= (others => '0'); |
||||
jtag_req <= '0'; |
||||
request <= (others => '0'); |
||||
elsif rising_edge(jtag_tck) then |
||||
|
||||
-- Handle jtag "commands" when sel is 1 |
||||
if sel = '1' then |
||||
-- Shift state, rotate the register |
||||
if shift = '1' then |
||||
shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1); |
||||
end if; |
||||
|
||||
-- Update state (trigger) |
||||
-- |
||||
-- Latch the request if we aren't already processing one and |
||||
-- it has a valid command opcode. |
||||
-- |
||||
if update = '1' and op_valid = '1' then |
||||
if jtag_bsy = '0' then |
||||
request <= shiftr; |
||||
jtag_req <= '1'; |
||||
end if; |
||||
-- Set the shift register "op" to "busy". This will prevent |
||||
-- us from re-starting the command on the next update if |
||||
-- the command completes before that. |
||||
shiftr(1 downto 0) <= DMI_RSP_BSY; |
||||
end if; |
||||
|
||||
-- Request completion. |
||||
-- |
||||
-- Capture the response data for reads and clear request flag. |
||||
-- |
||||
-- Note: We clear req (and thus dmi_req) here which relies on tck |
||||
-- ticking and sel set. This means we are stuck with dmi_req up if |
||||
-- the jtag interface stops. Slaves must be resilient to this. |
||||
-- |
||||
if jtag_req = '1' and dmi_ack_1 = '1' then |
||||
jtag_req <= '0'; |
||||
if request(1 downto 0) = DMI_REQ_RD then |
||||
request(DBITS + 1 downto 2) <= dmi_din; |
||||
end if; |
||||
end if; |
||||
|
||||
-- Capture state, grab latch content with updated status |
||||
if capture = '1' then |
||||
shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op; |
||||
end if; |
||||
|
||||
end if; |
||||
end if; |
||||
end process; |
||||
end architecture behaviour; |
@ -0,0 +1,337 @@
@@ -0,0 +1,337 @@
|
||||
4800012c |
||||
00000000 |
||||
08000048 |
||||
a600607d |
||||
05009f42 |
||||
14004a39 |
||||
a64b7b7d |
||||
480000f4 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
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00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
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00000000 |
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00000000 |
||||
00000000 |
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00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
08000048 |
||||
a600607d |
||||
05009f42 |
||||
14004a39 |
||||
a64b7b7d |
||||
48000004 |
||||
60210000 |
||||
64210000 |
||||
3d800000 |
||||
798c07c6 |
||||
618c0414 |
||||
4e800421 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
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00000000 |
||||
00000000 |
||||
00000000 |
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00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
ebc1fff0 |
||||
ebe1fff8 |
||||
4e800020 |
||||
38428a00 |
||||
fbe1fff8 |
||||
f821ffd1 |
||||
60000000 |
||||
38628000 |
||||
60000000 |
||||
60000000 |
||||
5463063e |
||||
480000b9 |
||||
2c1f000d |
||||
3860000a |
||||
60000000 |
||||
00000000 |
||||
00000180 |
||||
38428a00 |
||||
89228090 |
||||
39428088 |
||||
41820030 |
||||
39290014 |
||||
7d204eaa |
||||
4182ffec |
||||
7c0004ac |
||||
5463063e |
||||
e92a0000 |
||||
7c0004ac |
||||
71290001 |
||||
e86a0000 |
||||
7c0004ac |
||||
4bffffd0 |
||||
00000000 |
||||
3c400001 |
||||
60000000 |
||||
60000000 |
||||
2c090000 |
||||
e92a0000 |
||||
7c0004ac |
||||
71290020 |
||||
e92a0000 |
||||
7c604faa |
||||
e92a0000 |
||||
7c0004ac |
||||
71290008 |
||||
5469063e |
||||
7c0004ac |
||||
4e800020 |
||||
00000000 |
||||
3c400001 |
||||
7c0802a6 |
||||
fbc1fff0 |
||||
f8010010 |
||||
8fdf0001 |
||||
40820010 |
||||
38600000 |
||||
281e000a |
||||
3860000d |
||||
7fc3f378 |
||||
4bffffd0 |
||||
01000000 |
||||
7c691b78 |
||||
7d4918ae |
||||
4d820020 |
||||
4bfffff0 |
||||
00000000 |
||||
3c400001 |
||||
3d40c000 |
||||
794a0020 |
||||
7d4056ea |
||||
794a0600 |
||||
79290020 |
||||
7d204eea |
||||
41820018 |
||||
61290040 |
||||
7c0004ac |
||||
7929f804 |
||||
79290fc3 |
||||
79080020 |
||||
f9028088 |
||||
61082000 |
||||
41820084 |
||||
39200001 |
||||
3d00c000 |
||||
3920ff80 |
||||
7c0004ac |
||||
e9228088 |
||||
7d404faa |
||||
794ac202 |
||||
7c0004ac |
||||
e9228088 |
||||
3929000c |
||||
7d404faa |
||||
39290010 |
||||
7d404faa |
||||
39400007 |
||||
7c0004ac |
||||
4e800020 |
||||
394affff |
||||
3d20c000 |
||||
79290020 |
||||
7d404fea |
||||
00000000 |
||||
00000000 |
||||
38428a00 |
||||
89228090 |
||||
2f890000 |
||||
e9228088 |
||||
41820024 |
||||
2c230000 |
||||
614a0001 |
||||
7c0004ac |
||||
4e800020 |
||||
4bffffe0 |
||||
60630002 |
||||
7c0004ac |
||||
4e800020 |
||||
00000000 |
||||
00000010 |
||||
00527a01 |
||||
00010c1b |
||||
00000018 |
||||
00000070 |
||||
9f7e4111 |
||||
00000010 |
||||
00527a01 |
||||
00010c1b |
||||
00000018 |
||||
00000084 |
||||
00000010 |
||||
fffffcf8 |
||||
00000000 |
||||
00000040 |
||||
00000060 |
||||
9e019f00 |
||||
447e4111 |
||||
4106dedf |
||||
00000010 |
||||
fffffd98 |
||||
00000000 |
||||
00000080 |
||||
0000012c |
||||
00000010 |
||||
fffffec4 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
00000000 |
||||
2020200a |
||||
20202e6f |
||||
20222e20 |
||||
202e2220 |
||||
776d2e20 |
||||
4d202020 |
||||
74746177 |
||||
726f7720 |
||||
202e2020 |
||||
20202e20 |
||||
205c2020 |
||||
20202020 |
||||
2e2e3b20 |
||||
0a202020 |
||||
3b2e2e3b |
||||
200a2020 |
||||
20277777 |
@ -0,0 +1,63 @@
@@ -0,0 +1,63 @@
|
||||
library ieee; |
||||
use ieee.std_logic_1164.all; |
||||
|
||||
library work; |
||||
|
||||
entity main_bram is |
||||
generic( |
||||
WIDTH : natural := 64; |
||||
HEIGHT_BITS : natural := 11; |
||||
MEMORY_SIZE : natural := (8*1024); |
||||
RAM_INIT_FILE : string |
||||
); |
||||
port( |
||||
clk : in std_logic; |
||||
addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ; |
||||
di : in std_logic_vector(WIDTH-1 downto 0); |
||||
do : out std_logic_vector(WIDTH-1 downto 0); |
||||
sel : in std_logic_vector((WIDTH/8)-1 downto 0); |
||||
re : in std_ulogic; |
||||
we : in std_ulogic |
||||
); |
||||
end entity main_bram; |
||||
|
||||
architecture behaviour of main_bram is |
||||
component RAM_512x64 port ( |
||||
CLK : in std_ulogic; |
||||
WE : in std_ulogic_vector(7 downto 0); |
||||
EN : in std_ulogic; |
||||
Di : in std_ulogic_vector(63 downto 0); |
||||
Do : out std_ulogic_vector(63 downto 0); |
||||
A : in std_ulogic_vector(8 downto 0) |
||||
); |
||||
end component; |
||||
|
||||
signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0); |
||||
|
||||
signal obuf : std_logic_vector(WIDTH-1 downto 0); |
||||
begin |
||||
assert WIDTH = 64; |
||||
-- Do we have a log2 round up issue here? |
||||
assert HEIGHT_BITS = 10; |
||||
assert MEMORY_SIZE = (4*1024); |
||||
|
||||
sel_qual <= sel when we = '1' else (others => '0'); |
||||
|
||||
memory_0 : RAM_512x64 |
||||
port map ( |
||||
CLK => clk, |
||||
WE => sel_qual(7 downto 0), |
||||
EN => re or we, |
||||
Di => di(63 downto 0), |
||||
Do => obuf(63 downto 0), |
||||
A => addr(8 downto 0) |
||||
); |
||||
|
||||
-- The wishbone BRAM wrapper assumes a 1 cycle delay |
||||
memory_read_buffer: process(clk) |
||||
begin |
||||
if rising_edge(clk) then |
||||
do <= obuf; |
||||
end if; |
||||
end process; |
||||
end architecture behaviour; |
@ -0,0 +1,232 @@
@@ -0,0 +1,232 @@
|
||||
library ieee; |
||||
use ieee.std_logic_1164.all; |
||||
use ieee.numeric_std.all; |
||||
|
||||
library work; |
||||
use work.wishbone_types.all; |
||||
|
||||
entity toplevel is |
||||
generic ( |
||||
MEMORY_SIZE : integer := 8192; |
||||
RAM_INIT_FILE : string := "firmware.hex"; |
||||
RESET_LOW : boolean := true; |
||||
CLK_INPUT : positive := 100000000; |
||||
CLK_FREQUENCY : positive := 100000000; |
||||
HAS_FPU : boolean := false; |
||||
NO_BRAM : boolean := false; |
||||
DISABLE_FLATTEN_CORE : boolean := false; |
||||
SPI_FLASH_OFFSET : integer := 0; |
||||
SPI_FLASH_DEF_CKDV : natural := 4; |
||||
SPI_FLASH_DEF_QUAD : boolean := false; |
||||
LOG_LENGTH : natural := 0; |
||||
UART_IS_16550 : boolean := true; |
||||
HAS_UART1 : boolean := false; |
||||
HAS_JTAG : boolean := true; |
||||
INPUT_IOS : integer range 0 to 32 := 32; |
||||
OUTPUT_IOS : integer range 0 to 32 := 32 |
||||
); |
||||
port( |
||||
ext_clk : in std_ulogic; |
||||
ext_rst : in std_ulogic; |
||||
|
||||
-- UART0 signals: |
||||
uart0_txd : out std_ulogic; |
||||
uart0_rxd : in std_ulogic; |
||||
|
||||
-- UART1 signals: |
||||
uart1_txd : out std_ulogic; |
||||
uart1_rxd : in std_ulogic; |
||||
|
||||
-- SPI |
||||
spi_flash_cs_n : out std_ulogic; |
||||
spi_flash_clk : out std_ulogic; |
||||
spi_flash_sdat_i : in std_ulogic_vector(3 downto 0); |
||||
spi_flash_sdat_o : out std_ulogic_vector(3 downto 0); |
||||
spi_flash_sdat_oe : out std_ulogic_vector(3 downto 0); |
||||
|
||||
-- JTAG signals: |
||||
jtag_tck : in std_ulogic; |
||||
jtag_tdi : in std_ulogic; |
||||
jtag_tms : in std_ulogic; |
||||
jtag_trst : in std_ulogic; |
||||
jtag_tdo : out std_ulogic; |
||||
|
||||
-- Bill's bus |
||||
oib_clk : out std_ulogic; |
||||
ob_data : out std_ulogic_vector(7 downto 0); |
||||
ob_pty : out std_ulogic; |
||||
|
||||
ib_data : in std_ulogic_vector(7 downto 0); |
||||
ib_pty : in std_ulogic; |
||||
|
||||
-- IO Signals |
||||
gpio_out : out std_ulogic_vector(OUTPUT_IOS-1 downto 0); |
||||
gpio_in : in std_ulogic_vector(INPUT_IOS-1 downto 0); |
||||
|
||||
-- Add an I/O pin to select fetching from flash on reset |
||||
alt_reset : in std_ulogic |
||||
); |
||||
end entity toplevel; |
||||
|
||||
architecture behaviour of toplevel is |
||||
-- reset signals |
||||
signal system_rst : std_ulogic; |
||||
|
||||
-- external bus wishbone connection |
||||
signal wb_dram_out : wishbone_master_out; |
||||
signal wb_dram_in : wishbone_slave_out; |
||||
|
||||
-- external bus |
||||
signal wb_mc_adr : wishbone_addr_type; |
||||
signal wb_mc_dat_o : wishbone_data_type; |
||||
signal wb_mc_cyc : std_ulogic; |
||||
signal wb_mc_stb : std_ulogic; |
||||
signal wb_mc_sel : wishbone_sel_type; |
||||
signal wb_mc_we : std_ulogic; |
||||
signal wb_mc_dat_i : wishbone_data_type; |
||||
signal wb_mc_ack : std_ulogic; |
||||
signal wb_mc_stall : std_ulogic; |
||||
|
||||
signal wb_logic_analyzer_out : wb_io_slave_out := wb_io_slave_out_init; |
||||
signal wb_logic_analyzer_in : wb_io_master_out; |
||||
|
||||
signal wb_ext_io_in : wb_io_master_out; |
||||
signal wb_ext_io_out : wb_io_slave_out; |
||||
signal wb_ext_is_eth : std_ulogic; |
||||
|
||||
begin |
||||
|
||||
system_rst <= not ext_rst when RESET_LOW else ext_rst; |
||||
|
||||
-- Main SoC |
||||
soc0: entity work.soc |
||||
generic map( |
||||
MEMORY_SIZE => MEMORY_SIZE, |
||||
RAM_INIT_FILE => RAM_INIT_FILE, |
||||
SIM => false, |
||||
CLK_FREQ => CLK_FREQUENCY, |
||||
HAS_FPU => HAS_FPU, |
||||
HAS_DRAM => true, |
||||
DRAM_SIZE => 0, |
||||
DRAM_INIT_SIZE => 0, |
||||
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, |
||||
HAS_SPI_FLASH => true, |
||||
SPI_FLASH_DLINES => 4, |
||||
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, |
||||
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, |
||||
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, |
||||
LOG_LENGTH => LOG_LENGTH, |
||||
UART0_IS_16550 => UART_IS_16550, |
||||
HAS_UART1 => HAS_UART1, |
||||
HAS_JTAG => HAS_JTAG, |
||||
HAS_LITEETH => true |
||||
) |
||||
port map ( |
||||
-- System signals |
||||
system_clk => ext_clk, |
||||
rst => system_rst, |
||||
|
||||
-- UART signals |
||||
uart0_txd => uart0_txd, |
||||
uart0_rxd => uart0_rxd, |
||||
|
||||
-- UART1 signals |
||||
uart1_txd => uart1_txd, |
||||
uart1_rxd => uart1_rxd, |
||||
|
||||
-- SPI signals |
||||
spi_flash_sck => spi_flash_clk, |
||||
spi_flash_cs_n => spi_flash_cs_n, |
||||
spi_flash_sdat_o => spi_flash_sdat_o, |
||||
spi_flash_sdat_oe => spi_flash_sdat_oe, |
||||
spi_flash_sdat_i => spi_flash_sdat_i, |
||||
|
||||
-- JTAG signals |
||||
jtag_tck => jtag_tck, |
||||
jtag_tdi => jtag_tdi, |
||||
jtag_tms => jtag_tms, |
||||
jtag_trst => jtag_trst, |
||||
jtag_tdo => jtag_tdo, |
||||
|
||||
-- Use DRAM wishbone for Bill's bus |
||||
wb_dram_in => wb_dram_out, |
||||
wb_dram_out => wb_dram_in, |
||||
|
||||
wb_ext_io_in => wb_ext_io_in, |
||||
wb_ext_io_out => wb_ext_io_out, |
||||
wb_ext_is_eth => wb_ext_is_eth, |
||||
|
||||
-- Reset PC to flash offset 0 (ie 0xf000000) |
||||
alt_reset => alt_reset |
||||
); |
||||
|
||||
mc0: entity work.mc |
||||
generic map( |
||||
WB_AW => 32, -- wishbone_addr_bits |
||||
WB_DW => 64, -- wishbone_data_bits |
||||
OIB_DW => 8, |
||||
OIB_RATIO => 2, -- bill said this |
||||
BAR_INIT => x"1fff" -- dram has 512 bit space. CPU gives |
||||
-- top 3 bits as 0. carve off small |
||||
-- chunk at top for config space. |
||||
) |
||||
port map ( |
||||
clk => ext_clk, |
||||
rst => system_rst, |
||||
|
||||
wb_cyc => wb_mc_cyc, |
||||
wb_stb => wb_mc_stb, |
||||
wb_we => wb_mc_we, |
||||
wb_addr => wb_mc_adr, |
||||
wb_wr_data => wb_mc_dat_o, |
||||
wb_sel => wb_mc_sel, |
||||
wb_ack => wb_mc_ack, |
||||
-- wb_err => wb_mc_err, ?? |
||||
wb_stall => wb_mc_stall, |
||||
wb_rd_data => wb_mc_dat_i, |
||||
oib_clk => oib_clk, |
||||
ob_data => ob_data, |
||||
ob_pty => ob_pty, |
||||
ib_data => ib_data, |
||||
ib_pty => ib_pty |
||||
-- err => ob _err, |
||||
-- int => ob int |
||||
); |
||||
|
||||
logic_analyzer: entity work.logic_analyzer |
||||
generic map( |
||||
INPUT_IOS => INPUT_IOS, |
||||
OUTPUT_IOS => OUTPUT_IOS |
||||
) |
||||
port map( |
||||
clk => ext_clk, |
||||
rst => system_rst, |
||||
wb_in => wb_logic_analyzer_in, |
||||
wb_out => wb_logic_analyzer_out, |
||||
io_in => gpio_in, |
||||
io_out => gpio_out |
||||
); |
||||
|
||||
wb_logic_analyzer_in.adr <= wb_ext_io_in.adr; |
||||
wb_logic_analyzer_in.dat <= wb_ext_io_in.dat; |
||||
wb_logic_analyzer_in.cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; |
||||
wb_logic_analyzer_in.stb <= wb_ext_io_in.stb; |
||||
wb_logic_analyzer_in.sel <= wb_ext_io_in.sel; |
||||
wb_logic_analyzer_in.we <= wb_ext_io_in.we; |
||||
|
||||
wb_ext_io_out <= wb_logic_analyzer_out; |
||||
|
||||
|
||||
-- External bus wishbone |
||||
wb_mc_adr <= wb_dram_out.adr; |
||||
wb_mc_dat_o <= wb_dram_out.dat; |
||||
wb_mc_cyc <= wb_dram_out.cyc; |
||||
wb_mc_stb <= wb_dram_out.stb; |
||||
wb_mc_sel <= wb_dram_out.sel; |
||||
wb_mc_we <= wb_dram_out.we; |
||||
|
||||
wb_dram_in.dat <= wb_mc_dat_i; |
||||
wb_dram_in.ack <= wb_mc_ack; |
||||
wb_dram_in.stall <= wb_mc_stall; |
||||
|
||||
end architecture behaviour; |
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