forked from cores/microwatt
Compare commits
No commits in common. 'master' and 'orange-crab-freq' have entirely different histories.
master
...
orange-cra
@ -1,225 +0,0 @@
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LOCATE COMP "ext_clk" SITE "A9";
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IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
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// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13
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// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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// user_button as reset
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LOCATE COMP "ext_rst_n" SITE "J17";
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IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I;
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LOCATE COMP "usb_d_p" SITE "N1";
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LOCATE COMP "usb_d_n" SITE "M2";
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LOCATE COMP "usb_pullup" SITE "N2";
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IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
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IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
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IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
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LOCATE COMP "led0_g" SITE "M3";
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LOCATE COMP "led0_r" SITE "K4";
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LOCATE COMP "led0_b" SITE "J3";
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IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
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IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
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IOBUF PORT "led0_b" IO_TYPE=LVCMOS33;
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// discontinuous gpio numbers, match orangecrab litex platform
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LOCATE COMP "pin_gpio_0" SITE "N17"; // tx
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LOCATE COMP "pin_gpio_1" SITE "M18"; // rx
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LOCATE COMP "pin_gpio_2" SITE "C10"; // sda
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LOCATE COMP "pin_gpio_3" SITE "C9"; // scl
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//
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LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5
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LOCATE COMP "pin_gpio_6" SITE "B9"; // ...
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//
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LOCATE COMP "pin_gpio_9" SITE "C8"; //
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LOCATE COMP "pin_gpio_10" SITE "B8"; //
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LOCATE COMP "pin_gpio_11" SITE "A8"; //
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LOCATE COMP "pin_gpio_12" SITE "H2"; //
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LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13
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LOCATE COMP "pin_gpio_14" SITE "N15"; // miso
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LOCATE COMP "pin_gpio_15" SITE "R17"; // sck
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LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi
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LOCATE COMP "pin_io_a0" SITE "L4";
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LOCATE COMP "pin_io_a1" SITE "N3";
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LOCATE COMP "pin_io_a2" SITE "N4";
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LOCATE COMP "pin_io_a3" SITE "H4";
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LOCATE COMP "pin_io_a4" SITE "G4";
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LOCATE COMP "pin_io_a5" SITE "T17";
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IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33;
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IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33;
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LOCATE COMP "ddram_a[0]" SITE "C4";
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LOCATE COMP "ddram_a[1]" SITE "D2";
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LOCATE COMP "ddram_a[2]" SITE "D3";
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LOCATE COMP "ddram_a[3]" SITE "A3";
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LOCATE COMP "ddram_a[4]" SITE "A4";
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LOCATE COMP "ddram_a[5]" SITE "D4";
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LOCATE COMP "ddram_a[6]" SITE "C3";
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LOCATE COMP "ddram_a[7]" SITE "B2";
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LOCATE COMP "ddram_a[8]" SITE "B1";
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LOCATE COMP "ddram_a[9]" SITE "D1";
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LOCATE COMP "ddram_a[10]" SITE "A7";
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LOCATE COMP "ddram_a[11]" SITE "C2";
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LOCATE COMP "ddram_a[12]" SITE "B6";
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LOCATE COMP "ddram_a[13]" SITE "C1";
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LOCATE COMP "ddram_a[14]" SITE "A2";
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LOCATE COMP "ddram_a[15]" SITE "C7";
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IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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LOCATE COMP "ddram_ba[0]" SITE "D6";
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LOCATE COMP "ddram_ba[1]" SITE "B7";
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LOCATE COMP "ddram_ba[2]" SITE "A6";
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LOCATE COMP "ddram_cas_n" SITE "D13";
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LOCATE COMP "ddram_cs_n" SITE "A12";
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LOCATE COMP "ddram_dm[0]" SITE "D16";
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LOCATE COMP "ddram_dm[1]" SITE "G16";
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LOCATE COMP "ddram_ras_n" SITE "C12";
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LOCATE COMP "ddram_we_n" SITE "B12";
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IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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// from litex platform, termination disabled to reduce heat
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LOCATE COMP "ddram_dq[0]" SITE "C17";
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LOCATE COMP "ddram_dq[1]" SITE "D15";
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LOCATE COMP "ddram_dq[2]" SITE "B17";
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LOCATE COMP "ddram_dq[3]" SITE "C16";
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LOCATE COMP "ddram_dq[4]" SITE "A15";
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LOCATE COMP "ddram_dq[5]" SITE "B13";
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LOCATE COMP "ddram_dq[6]" SITE "A17";
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LOCATE COMP "ddram_dq[7]" SITE "A13";
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LOCATE COMP "ddram_dq[8]" SITE "F17";
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LOCATE COMP "ddram_dq[9]" SITE "F16";
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LOCATE COMP "ddram_dq[10]" SITE "G15";
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LOCATE COMP "ddram_dq[11]" SITE "F15";
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LOCATE COMP "ddram_dq[12]" SITE "J16";
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LOCATE COMP "ddram_dq[13]" SITE "C18";
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LOCATE COMP "ddram_dq[14]" SITE "H16";
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LOCATE COMP "ddram_dq[15]" SITE "F18";
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IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
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LOCATE COMP "ddram_dqs_n[0]" SITE "A16";
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LOCATE COMP "ddram_dqs_n[1]" SITE "H17";
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LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
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LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
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IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
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LOCATE COMP "ddram_clk_p" SITE "J18";
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LOCATE COMP "ddram_clk_n" SITE "K18";
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IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
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IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
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LOCATE COMP "ddram_cke" SITE "D18";
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LOCATE COMP "ddram_odt" SITE "C13";
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LOCATE COMP "ddram_reset_n" SITE "L18";
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IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
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LOCATE COMP "ddram_vccio[0]" SITE "K16";
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LOCATE COMP "ddram_vccio[1]" SITE "D17";
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LOCATE COMP "ddram_vccio[2]" SITE "K15";
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LOCATE COMP "ddram_vccio[3]" SITE "K17";
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LOCATE COMP "ddram_vccio[4]" SITE "B18";
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LOCATE COMP "ddram_vccio[5]" SITE "C6";
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LOCATE COMP "ddram_gnd[0]" SITE "L15";
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LOCATE COMP "ddram_gnd[1]" SITE "L16";
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IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
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// We use USRMCLK instead for clk
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// LOCATE COMP "spi_flash_clk" SITE "U16";
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// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_cs_n" SITE "U17";
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IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_mosi" SITE "U18";
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IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_miso" SITE "T18";
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IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_wp_n" SITE "R18";
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IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "spi_flash_hold_n" SITE "N18";
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IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
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LOCATE COMP "sdcard_data[0]" SITE "J1";
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LOCATE COMP "sdcard_data[1]" SITE "K3";
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LOCATE COMP "sdcard_data[2]" SITE "L3";
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LOCATE COMP "sdcard_data[3]" SITE "M1";
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LOCATE COMP "sdcard_cmd" SITE "K2";
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LOCATE COMP "sdcard_clk" SITE "K1";
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LOCATE COMP "sdcard_cd" SITE "L1";
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IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
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IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
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IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33;
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@ -1,136 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.helpers.all;
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entity bit_counter is
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port (
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clk : in std_logic;
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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do_popcnt : in std_ulogic;
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is_32bit : in std_ulogic;
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datalen : in std_ulogic_vector(3 downto 0);
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity bit_counter;
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architecture behaviour of bit_counter is
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-- signals for count-leading/trailing-zeroes
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signal inp : std_ulogic_vector(63 downto 0);
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signal inp_r : std_ulogic_vector(63 downto 0);
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signal sum : std_ulogic_vector(64 downto 0);
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signal sum_r : std_ulogic_vector(64 downto 0);
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signal onehot : std_ulogic_vector(63 downto 0);
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signal edge : std_ulogic_vector(63 downto 0);
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signal bitnum : std_ulogic_vector(5 downto 0);
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signal cntz : std_ulogic_vector(63 downto 0);
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-- signals for popcnt
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signal dlen_r : std_ulogic_vector(3 downto 0);
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signal pcnt_r : std_ulogic;
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subtype twobit is unsigned(1 downto 0);
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type twobit32 is array(0 to 31) of twobit;
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signal pc2 : twobit32;
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subtype threebit is unsigned(2 downto 0);
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type threebit16 is array(0 to 15) of threebit;
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signal pc4 : threebit16;
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subtype fourbit is unsigned(3 downto 0);
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type fourbit8 is array(0 to 7) of fourbit;
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signal pc8 : fourbit8;
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signal pc8_r : fourbit8;
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subtype sixbit is unsigned(5 downto 0);
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type sixbit2 is array(0 to 1) of sixbit;
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signal pc32 : sixbit2;
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signal popcnt : std_ulogic_vector(63 downto 0);
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begin
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countzero_r: process(clk)
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begin
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if rising_edge(clk) then
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inp_r <= inp;
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sum_r <= sum;
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end if;
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end process;
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countzero: process(all)
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variable bitnum_e, bitnum_o : std_ulogic_vector(5 downto 0);
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begin
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if is_32bit = '0' then
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if count_right = '0' then
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inp <= bit_reverse(rs);
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else
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inp <= rs;
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end if;
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else
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inp(63 downto 32) <= x"FFFFFFFF";
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if count_right = '0' then
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inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
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else
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inp(31 downto 0) <= rs(31 downto 0);
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end if;
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end if;
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sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
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|
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-- The following occurs after a clock edge
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edge <= sum_r(63 downto 0) or inp_r;
|
||||
bitnum_e := edgelocation(edge, 6);
|
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onehot <= sum_r(63 downto 0) and inp_r;
|
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bitnum_o := bit_number(onehot);
|
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bitnum(5 downto 2) <= bitnum_e(5 downto 2);
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bitnum(1 downto 0) <= bitnum_o(1 downto 0);
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cntz <= 57x"0" & sum_r(64) & bitnum;
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end process;
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popcnt_r: process(clk)
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begin
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if rising_edge(clk) then
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for i in 0 to 7 loop
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pc8_r(i) <= pc8(i);
|
||||
end loop;
|
||||
dlen_r <= datalen;
|
||||
pcnt_r <= do_popcnt;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
popcnt_a: process(all)
|
||||
begin
|
||||
for i in 0 to 31 loop
|
||||
pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
|
||||
end loop;
|
||||
for i in 0 to 15 loop
|
||||
pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
|
||||
end loop;
|
||||
for i in 0 to 7 loop
|
||||
pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
|
||||
end loop;
|
||||
|
||||
-- after a clock edge
|
||||
for i in 0 to 1 loop
|
||||
pc32(i) <= ("00" & pc8_r(i * 4)) + ("00" & pc8_r(i * 4 + 1)) +
|
||||
("00" & pc8_r(i * 4 + 2)) + ("00" & pc8_r(i * 4 + 3));
|
||||
end loop;
|
||||
|
||||
popcnt <= (others => '0');
|
||||
if dlen_r(3 downto 2) = "00" then
|
||||
-- popcntb
|
||||
for i in 0 to 7 loop
|
||||
popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8_r(i));
|
||||
end loop;
|
||||
elsif dlen_r(3) = '0' then
|
||||
-- popcntw
|
||||
for i in 0 to 1 loop
|
||||
popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
|
||||
end loop;
|
||||
else
|
||||
popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
result <= cntz when pcnt_r = '0' else popcnt;
|
||||
|
||||
end behaviour;
|
||||
@ -0,0 +1,60 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.helpers.all;
|
||||
|
||||
entity zero_counter is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rs : in std_ulogic_vector(63 downto 0);
|
||||
count_right : in std_ulogic;
|
||||
is_32bit : in std_ulogic;
|
||||
result : out std_ulogic_vector(63 downto 0)
|
||||
);
|
||||
end entity zero_counter;
|
||||
|
||||
architecture behaviour of zero_counter is
|
||||
signal inp : std_ulogic_vector(63 downto 0);
|
||||
signal sum : std_ulogic_vector(64 downto 0);
|
||||
signal msb_r : std_ulogic;
|
||||
signal onehot : std_ulogic_vector(63 downto 0);
|
||||
signal onehot_r : std_ulogic_vector(63 downto 0);
|
||||
signal bitnum : std_ulogic_vector(5 downto 0);
|
||||
|
||||
begin
|
||||
countzero_r: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
msb_r <= sum(64);
|
||||
onehot_r <= onehot;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
countzero: process(all)
|
||||
begin
|
||||
if is_32bit = '0' then
|
||||
if count_right = '0' then
|
||||
inp <= bit_reverse(rs);
|
||||
else
|
||||
inp <= rs;
|
||||
end if;
|
||||
else
|
||||
inp(63 downto 32) <= x"FFFFFFFF";
|
||||
if count_right = '0' then
|
||||
inp(31 downto 0) <= bit_reverse(rs(31 downto 0));
|
||||
else
|
||||
inp(31 downto 0) <= rs(31 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
sum <= std_ulogic_vector(unsigned('0' & not inp) + 1);
|
||||
onehot <= sum(63 downto 0) and inp;
|
||||
|
||||
-- The following occurs after a clock edge
|
||||
bitnum <= bit_number(onehot_r);
|
||||
|
||||
result <= x"00000000000000" & "0" & msb_r & bitnum;
|
||||
end process;
|
||||
end behaviour;
|
||||
@ -1,298 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity dmi_dtm is
|
||||
generic(ABITS : INTEGER:=8;
|
||||
DBITS : INTEGER:=64);
|
||||
|
||||
port(sys_clk : in std_ulogic;
|
||||
sys_reset : in std_ulogic;
|
||||
dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
|
||||
dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
|
||||
dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
|
||||
dmi_req : out std_ulogic;
|
||||
dmi_wr : out std_ulogic;
|
||||
dmi_ack : in std_ulogic
|
||||
-- dmi_err : in std_ulogic TODO: Add error response
|
||||
);
|
||||
end entity dmi_dtm;
|
||||
|
||||
architecture behaviour of dmi_dtm is
|
||||
-- Signals coming out of the JTAGG block
|
||||
signal jtag_reset_n : std_ulogic;
|
||||
signal tdi : std_ulogic;
|
||||
signal tdo : std_ulogic;
|
||||
signal tck : std_ulogic;
|
||||
signal jce1 : std_ulogic;
|
||||
signal jshift : std_ulogic;
|
||||
signal update : std_ulogic;
|
||||
|
||||
-- signals to match dmi_dtb_xilinx
|
||||
signal jtag_reset : std_ulogic;
|
||||
signal capture : std_ulogic;
|
||||
signal jtag_clk : std_ulogic;
|
||||
signal sel : std_ulogic;
|
||||
signal shift : std_ulogic;
|
||||
|
||||
-- delays
|
||||
signal jce1_d : std_ulogic;
|
||||
constant TCK_DELAY : INTEGER := 8;
|
||||
signal tck_d : std_ulogic_vector(TCK_DELAY+1 downto 1);
|
||||
|
||||
-- ** JTAG clock domain **
|
||||
|
||||
-- Shift register
|
||||
signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
|
||||
|
||||
-- Latched request
|
||||
signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
|
||||
|
||||
-- A request is present
|
||||
signal jtag_req : std_ulogic;
|
||||
|
||||
-- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
|
||||
signal dmi_ack_0 : std_ulogic;
|
||||
signal dmi_ack_1 : std_ulogic;
|
||||
|
||||
-- ** sys clock domain **
|
||||
|
||||
-- Synchronizer for jtag_req (jtag clk -> sys clk)
|
||||
signal jtag_req_0 : std_ulogic;
|
||||
signal jtag_req_1 : std_ulogic;
|
||||
|
||||
-- ** combination signals
|
||||
signal jtag_bsy : std_ulogic;
|
||||
signal op_valid : std_ulogic;
|
||||
signal rsp_op : std_ulogic_vector(1 downto 0);
|
||||
|
||||
-- ** Constants **
|
||||
constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
|
||||
constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
|
||||
constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
|
||||
constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
|
||||
constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
|
||||
attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
|
||||
attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
|
||||
attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
|
||||
|
||||
-- ECP5 JTAGG
|
||||
component JTAGG is
|
||||
generic (
|
||||
ER1 : string := "ENABLED";
|
||||
ER2 : string := "ENABLED"
|
||||
);
|
||||
port(
|
||||
JTDO1 : in std_ulogic;
|
||||
JTDO2 : in std_ulogic;
|
||||
JTDI : out std_ulogic;
|
||||
JTCK : out std_ulogic;
|
||||
JRTI1 : out std_ulogic;
|
||||
JRTI2 : out std_ulogic;
|
||||
JSHIFT : out std_ulogic;
|
||||
JUPDATE : out std_ulogic;
|
||||
JRSTN : out std_ulogic;
|
||||
JCE1 : out std_ulogic;
|
||||
JCE2 : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
component LUT4 is
|
||||
generic (
|
||||
INIT : std_logic_vector
|
||||
);
|
||||
port(
|
||||
A : in STD_ULOGIC;
|
||||
B : in STD_ULOGIC;
|
||||
C : in STD_ULOGIC;
|
||||
D : in STD_ULOGIC;
|
||||
Z : out STD_ULOGIC
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
jtag: JTAGG
|
||||
generic map(
|
||||
ER2 => "DISABLED"
|
||||
)
|
||||
port map (
|
||||
JTDO1 => tdo,
|
||||
JTDO2 => '0',
|
||||
JTDI => tdi,
|
||||
JTCK => tck,
|
||||
JRTI1 => open,
|
||||
JRTI2 => open,
|
||||
JSHIFT => jshift,
|
||||
JUPDATE => update,
|
||||
JRSTN => jtag_reset_n,
|
||||
JCE1 => jce1,
|
||||
JCE2 => open
|
||||
);
|
||||
|
||||
-- JRTI1 looks like it could be connected to SEL, but
|
||||
-- in practise JRTI1 is only high briefly, not for the duration
|
||||
-- of the transmission. possibly mw_debug could be modified.
|
||||
-- The ecp5 is probably the only jtag device anyway.
|
||||
sel <= '1';
|
||||
|
||||
-- TDI needs to align with TCK, we use LUT delays here.
|
||||
-- From https://github.com/enjoy-digital/litex/pull/1087
|
||||
tck_d(1) <= tck;
|
||||
del: for i in 1 to TCK_DELAY generate
|
||||
attribute keep : boolean;
|
||||
attribute keep of l: label is true;
|
||||
begin
|
||||
l: LUT4
|
||||
generic map(
|
||||
INIT => b"0000_0000_0000_0010"
|
||||
)
|
||||
port map (
|
||||
A => tck_d(i),
|
||||
B => '0', C => '0', D => '0',
|
||||
Z => tck_d(i+1)
|
||||
);
|
||||
end generate;
|
||||
jtag_clk <= tck_d(TCK_DELAY+1);
|
||||
|
||||
-- capture signal
|
||||
jce1_sync : process(jtag_clk)
|
||||
begin
|
||||
if rising_edge(jtag_clk) then
|
||||
jce1_d <= jce1;
|
||||
capture <= jce1 and not jce1_d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- latch the shift signal, otherwise
|
||||
-- we miss the last shift in
|
||||
-- (maybe because we are delaying tck?)
|
||||
shift_sync : process(jtag_clk)
|
||||
begin
|
||||
if (sys_reset = '1') then
|
||||
shift <= '0';
|
||||
elsif rising_edge(jtag_clk) then
|
||||
shift <= jshift;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
jtag_reset <= not jtag_reset_n;
|
||||
|
||||
-- dmi_req synchronization
|
||||
dmi_req_sync : process(sys_clk)
|
||||
begin
|
||||
-- sys_reset is synchronous
|
||||
if rising_edge(sys_clk) then
|
||||
if (sys_reset = '1') then
|
||||
jtag_req_0 <= '0';
|
||||
jtag_req_1 <= '0';
|
||||
else
|
||||
jtag_req_0 <= jtag_req;
|
||||
jtag_req_1 <= jtag_req_0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmi_req <= jtag_req_1;
|
||||
|
||||
-- dmi_ack synchronization
|
||||
dmi_ack_sync: process(jtag_clk, jtag_reset)
|
||||
begin
|
||||
-- jtag_reset is async (see comments)
|
||||
if jtag_reset = '1' then
|
||||
dmi_ack_0 <= '0';
|
||||
dmi_ack_1 <= '0';
|
||||
elsif rising_edge(jtag_clk) then
|
||||
dmi_ack_0 <= dmi_ack;
|
||||
dmi_ack_1 <= dmi_ack_0;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- jtag_bsy indicates whether we can start a new request, we can when
|
||||
-- we aren't already processing one (jtag_req) and the synchronized ack
|
||||
-- of the previous one is 0.
|
||||
--
|
||||
jtag_bsy <= jtag_req or dmi_ack_1;
|
||||
|
||||
-- decode request type in shift register
|
||||
with shiftr(1 downto 0) select op_valid <=
|
||||
'1' when DMI_REQ_RD,
|
||||
'1' when DMI_REQ_WR,
|
||||
'0' when others;
|
||||
|
||||
-- encode response op
|
||||
rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
|
||||
|
||||
-- Some DMI out signals are directly driven from the request register
|
||||
dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
|
||||
dmi_dout <= request(DBITS + 1 downto 2);
|
||||
dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
|
||||
|
||||
-- TDO is wired to shift register bit 0
|
||||
tdo <= shiftr(0);
|
||||
|
||||
-- Main state machine. Handles shift registers, request latch and
|
||||
-- jtag_req latch. Could be split into 3 processes but it's probably
|
||||
-- not worthwhile.
|
||||
--
|
||||
shifter: process(jtag_clk, jtag_reset, sys_reset)
|
||||
begin
|
||||
if jtag_reset = '1' or sys_reset = '1' then
|
||||
shiftr <= (others => '0');
|
||||
jtag_req <= '0';
|
||||
request <= (others => '0');
|
||||
elsif rising_edge(jtag_clk) then
|
||||
|
||||
-- Handle jtag "commands" when sel is 1
|
||||
if sel = '1' then
|
||||
-- Shift state, rotate the register
|
||||
if shift = '1' then
|
||||
shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
|
||||
end if;
|
||||
|
||||
-- Update state (trigger)
|
||||
--
|
||||
-- Latch the request if we aren't already processing one and
|
||||
-- it has a valid command opcode.
|
||||
--
|
||||
if update = '1' and op_valid = '1' then
|
||||
if jtag_bsy = '0' then
|
||||
request <= shiftr;
|
||||
jtag_req <= '1';
|
||||
end if;
|
||||
-- Set the shift register "op" to "busy". This will prevent
|
||||
-- us from re-starting the command on the next update if
|
||||
-- the command completes before that.
|
||||
shiftr(1 downto 0) <= DMI_RSP_BSY;
|
||||
end if;
|
||||
|
||||
-- Request completion.
|
||||
--
|
||||
-- Capture the response data for reads and clear request flag.
|
||||
--
|
||||
-- Note: We clear req (and thus dmi_req) here which relies on tck
|
||||
-- ticking and sel set. This means we are stuck with dmi_req up if
|
||||
-- the jtag interface stops. Slaves must be resilient to this.
|
||||
--
|
||||
if jtag_req = '1' and dmi_ack_1 = '1' then
|
||||
jtag_req <= '0';
|
||||
if request(1 downto 0) = DMI_REQ_RD then
|
||||
request(DBITS + 1 downto 2) <= dmi_din;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Capture state, grab latch content with updated status
|
||||
if capture = '1' then
|
||||
shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end architecture behaviour;
|
||||
|
||||
@ -1,512 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity toplevel is
|
||||
generic (
|
||||
MEMORY_SIZE : integer := 16384;
|
||||
RAM_INIT_FILE : string := "firmware.hex";
|
||||
RESET_LOW : boolean := true;
|
||||
CLK_INPUT : positive := 100000000;
|
||||
CLK_FREQUENCY : positive := 100000000;
|
||||
HAS_FPU : boolean := true;
|
||||
HAS_BTC : boolean := false;
|
||||
USE_LITEDRAM : boolean := true;
|
||||
NO_BRAM : boolean := true;
|
||||
SCLK_STARTUPE2 : boolean := false;
|
||||
SPI_FLASH_OFFSET : integer := 4194304;
|
||||
SPI_FLASH_DEF_CKDV : natural := 1;
|
||||
SPI_FLASH_DEF_QUAD : boolean := true;
|
||||
LOG_LENGTH : natural := 0;
|
||||
UART_IS_16550 : boolean := true;
|
||||
HAS_UART1 : boolean := false;
|
||||
USE_LITESDCARD : boolean := true;
|
||||
ICACHE_NUM_LINES : natural := 64;
|
||||
NGPIO : natural := 0
|
||||
);
|
||||
port(
|
||||
ext_clk : in std_ulogic;
|
||||
ext_rst_n : in std_ulogic;
|
||||
|
||||
-- UART0 signals:
|
||||
pin_gpio_0 : out std_ulogic;
|
||||
pin_gpio_1 : in std_ulogic;
|
||||
|
||||
-- LEDs
|
||||
led0_b : out std_ulogic;
|
||||
led0_g : out std_ulogic;
|
||||
led0_r : out std_ulogic;
|
||||
|
||||
-- SPI
|
||||
spi_flash_cs_n : out std_ulogic;
|
||||
spi_flash_mosi : inout std_ulogic;
|
||||
spi_flash_miso : inout std_ulogic;
|
||||
spi_flash_wp_n : inout std_ulogic;
|
||||
spi_flash_hold_n : inout std_ulogic;
|
||||
|
||||
-- SD card wires
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
|
||||
-- DRAM wires
|
||||
ddram_a : out std_ulogic_vector(13 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_cs_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic_vector(0 downto 0);
|
||||
-- only the positive differential pin is instantiated
|
||||
--ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
--ddram_clk_n : out std_ulogic_vector(0 downto 0);
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic;
|
||||
|
||||
ddram_gnd : out std_ulogic_vector(1 downto 0);
|
||||
ddram_vccio : out std_ulogic_vector(5 downto 0)
|
||||
);
|
||||
end entity toplevel;
|
||||
|
||||
architecture behaviour of toplevel is
|
||||
|
||||
-- Reset signals:
|
||||
signal soc_rst : std_ulogic;
|
||||
signal pll_rst : std_ulogic;
|
||||
|
||||
-- Internal clock signals:
|
||||
signal system_clk : std_ulogic;
|
||||
signal system_clk_locked : std_ulogic;
|
||||
|
||||
-- External IOs from the SoC
|
||||
signal wb_ext_io_in : wb_io_master_out;
|
||||
signal wb_ext_io_out : wb_io_slave_out;
|
||||
signal wb_ext_is_dram_csr : std_ulogic;
|
||||
signal wb_ext_is_dram_init : std_ulogic;
|
||||
signal wb_ext_is_sdcard : std_ulogic;
|
||||
|
||||
-- DRAM main data wishbone connection
|
||||
signal wb_dram_in : wishbone_master_out;
|
||||
signal wb_dram_out : wishbone_slave_out;
|
||||
|
||||
-- DRAM control wishbone connection
|
||||
signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
|
||||
-- LiteSDCard connection
|
||||
signal ext_irq_sdcard : std_ulogic := '0';
|
||||
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
|
||||
signal wb_sddma_in : wb_io_slave_out;
|
||||
signal wb_sddma_nr : wb_io_master_out;
|
||||
signal wb_sddma_ir : wb_io_slave_out;
|
||||
-- for conversion from non-pipelined wishbone to pipelined
|
||||
signal wb_sddma_stb_sent : std_ulogic;
|
||||
|
||||
-- Control/status
|
||||
signal core_alt_reset : std_ulogic;
|
||||
|
||||
-- Status LED
|
||||
signal led0_b_pwm : std_ulogic;
|
||||
signal led0_r_pwm : std_ulogic;
|
||||
signal led0_g_pwm : std_ulogic;
|
||||
|
||||
-- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
|
||||
signal pwm_counter : std_ulogic_vector(8 downto 0);
|
||||
|
||||
-- SPI flash
|
||||
signal spi_sck : std_ulogic;
|
||||
signal spi_cs_n : std_ulogic;
|
||||
signal spi_sdat_o : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_i : std_ulogic_vector(3 downto 0);
|
||||
|
||||
-- GPIO
|
||||
signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
|
||||
-- Fixup various memory sizes based on generics
|
||||
function get_bram_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return 0;
|
||||
else
|
||||
return MEMORY_SIZE;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
function get_payload_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return MEMORY_SIZE;
|
||||
else
|
||||
return 0;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
constant BRAM_SIZE : natural := get_bram_size;
|
||||
constant PAYLOAD_SIZE : natural := get_payload_size;
|
||||
|
||||
COMPONENT USRMCLK
|
||||
PORT(
|
||||
USRMCLKI : IN STD_ULOGIC;
|
||||
USRMCLKTS : IN STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
attribute syn_noprune: boolean ;
|
||||
attribute syn_noprune of USRMCLK: component is true;
|
||||
|
||||
begin
|
||||
|
||||
-- Main SoC
|
||||
soc0: entity work.soc
|
||||
generic map(
|
||||
MEMORY_SIZE => BRAM_SIZE,
|
||||
RAM_INIT_FILE => RAM_INIT_FILE,
|
||||
SIM => false,
|
||||
CLK_FREQ => CLK_FREQUENCY,
|
||||
HAS_FPU => HAS_FPU,
|
||||
HAS_BTC => HAS_BTC,
|
||||
HAS_DRAM => USE_LITEDRAM,
|
||||
DRAM_SIZE => 256 * 1024 * 1024,
|
||||
DRAM_INIT_SIZE => PAYLOAD_SIZE,
|
||||
HAS_SPI_FLASH => true,
|
||||
SPI_FLASH_DLINES => 4,
|
||||
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
|
||||
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
|
||||
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
|
||||
LOG_LENGTH => LOG_LENGTH,
|
||||
UART0_IS_16550 => UART_IS_16550,
|
||||
HAS_UART1 => HAS_UART1,
|
||||
HAS_SD_CARD => USE_LITESDCARD,
|
||||
ICACHE_NUM_LINES => ICACHE_NUM_LINES,
|
||||
HAS_SHORT_MULT => true,
|
||||
NGPIO => NGPIO
|
||||
)
|
||||
port map (
|
||||
-- System signals
|
||||
system_clk => system_clk,
|
||||
rst => soc_rst,
|
||||
|
||||
-- UART signals
|
||||
uart0_txd => pin_gpio_0,
|
||||
uart0_rxd => pin_gpio_1,
|
||||
|
||||
-- UART1 signals
|
||||
--uart1_txd => uart_pmod_tx,
|
||||
--uart1_rxd => uart_pmod_rx,
|
||||
|
||||
-- SPI signals
|
||||
spi_flash_sck => spi_sck,
|
||||
spi_flash_cs_n => spi_cs_n,
|
||||
spi_flash_sdat_o => spi_sdat_o,
|
||||
spi_flash_sdat_oe => spi_sdat_oe,
|
||||
spi_flash_sdat_i => spi_sdat_i,
|
||||
|
||||
-- GPIO signals
|
||||
gpio_in => gpio_in,
|
||||
gpio_out => gpio_out,
|
||||
gpio_dir => gpio_dir,
|
||||
|
||||
-- External interrupts
|
||||
ext_irq_sdcard => ext_irq_sdcard,
|
||||
|
||||
-- DRAM wishbone
|
||||
wb_dram_in => wb_dram_in,
|
||||
wb_dram_out => wb_dram_out,
|
||||
|
||||
-- IO wishbone
|
||||
wb_ext_io_in => wb_ext_io_in,
|
||||
wb_ext_io_out => wb_ext_io_out,
|
||||
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
|
||||
wb_ext_is_dram_init => wb_ext_is_dram_init,
|
||||
wb_ext_is_sdcard => wb_ext_is_sdcard,
|
||||
|
||||
-- DMA wishbone
|
||||
wishbone_dma_in => wb_sddma_in,
|
||||
wishbone_dma_out => wb_sddma_out,
|
||||
|
||||
alt_reset => core_alt_reset
|
||||
);
|
||||
|
||||
-- SPI Flash
|
||||
--
|
||||
spi_flash_cs_n <= spi_cs_n;
|
||||
spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
|
||||
spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
|
||||
spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
|
||||
spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
|
||||
spi_sdat_i(0) <= spi_flash_mosi;
|
||||
spi_sdat_i(1) <= spi_flash_miso;
|
||||
spi_sdat_i(2) <= spi_flash_wp_n;
|
||||
spi_sdat_i(3) <= spi_flash_hold_n;
|
||||
|
||||
uclk: USRMCLK port map (
|
||||
USRMCLKI => spi_sck,
|
||||
USRMCLKTS => '0'
|
||||
);
|
||||
|
||||
nodram: if not USE_LITEDRAM generate
|
||||
signal ddram_clk_dummy : std_ulogic;
|
||||
begin
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked,
|
||||
ext_rst_in => ext_rst_n,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => soc_rst
|
||||
);
|
||||
|
||||
clkgen: entity work.clock_generator
|
||||
generic map(
|
||||
CLK_INPUT_HZ => CLK_INPUT,
|
||||
CLK_OUTPUT_HZ => CLK_FREQUENCY
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_rst_in => pll_rst,
|
||||
pll_clk_out => system_clk,
|
||||
pll_locked_out => system_clk_locked
|
||||
);
|
||||
|
||||
led0_b_pwm <= '1';
|
||||
led0_r_pwm <= '1';
|
||||
led0_g_pwm <= '0';
|
||||
core_alt_reset <= '0';
|
||||
|
||||
end generate;
|
||||
|
||||
has_dram: if USE_LITEDRAM generate
|
||||
signal dram_init_done : std_ulogic;
|
||||
signal dram_init_error : std_ulogic;
|
||||
signal dram_sys_rst : std_ulogic;
|
||||
signal rst_gen_rst : std_ulogic;
|
||||
begin
|
||||
|
||||
-- Eventually dig out the frequency from
|
||||
-- litesdram generate.py sys_clk_freq
|
||||
-- but for now, assert it's 48Mhz for orangecrab
|
||||
assert CLK_FREQUENCY = 48000000;
|
||||
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW,
|
||||
PLL_RESET_BITS => 18,
|
||||
SOC_RESET_BITS => 1
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked,
|
||||
ext_rst_in => ext_rst_n,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => rst_gen_rst
|
||||
);
|
||||
|
||||
-- Generate SoC reset
|
||||
soc_rst_gen: process(system_clk)
|
||||
begin
|
||||
if ext_rst_n = '0' then
|
||||
soc_rst <= '1';
|
||||
elsif rising_edge(system_clk) then
|
||||
soc_rst <= dram_sys_rst or not system_clk_locked;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dram: entity work.litedram_wrapper
|
||||
generic map(
|
||||
DRAM_ABITS => 24,
|
||||
DRAM_ALINES => 14,
|
||||
DRAM_DLINES => 16,
|
||||
DRAM_CKLINES => 1,
|
||||
DRAM_PORT_WIDTH => 128,
|
||||
NUM_LINES => 8, -- reduce from default of 64 to make smaller/timing
|
||||
PAYLOAD_FILE => RAM_INIT_FILE,
|
||||
PAYLOAD_SIZE => PAYLOAD_SIZE
|
||||
)
|
||||
port map(
|
||||
clk_in => ext_clk,
|
||||
rst => pll_rst,
|
||||
system_clk => system_clk,
|
||||
system_reset => dram_sys_rst,
|
||||
core_alt_reset => core_alt_reset,
|
||||
pll_locked => system_clk_locked,
|
||||
|
||||
wb_in => wb_dram_in,
|
||||
wb_out => wb_dram_out,
|
||||
wb_ctrl_in => wb_ext_io_in,
|
||||
wb_ctrl_out => wb_dram_ctrl_out,
|
||||
wb_ctrl_is_csr => wb_ext_is_dram_csr,
|
||||
wb_ctrl_is_init => wb_ext_is_dram_init,
|
||||
|
||||
init_done => dram_init_done,
|
||||
init_error => dram_init_error,
|
||||
|
||||
ddram_a => ddram_a,
|
||||
ddram_ba => ddram_ba,
|
||||
ddram_ras_n => ddram_ras_n,
|
||||
ddram_cas_n => ddram_cas_n,
|
||||
ddram_we_n => ddram_we_n,
|
||||
ddram_cs_n => ddram_cs_n,
|
||||
ddram_dm => ddram_dm,
|
||||
ddram_dq => ddram_dq,
|
||||
ddram_dqs_p => ddram_dqs_p,
|
||||
ddram_clk_p => ddram_clk_p,
|
||||
-- only the positive differential pin is instantiated
|
||||
--ddram_dqs_n => ddram_dqs_n,
|
||||
--ddram_clk_n => ddram_clk_n,
|
||||
ddram_cke => ddram_cke,
|
||||
ddram_odt => ddram_odt,
|
||||
|
||||
ddram_reset_n => ddram_reset_n
|
||||
);
|
||||
|
||||
ddram_gnd <= "00";
|
||||
-- for power consumption.
|
||||
-- https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19#issuecomment-683479378
|
||||
ddram_vccio <= "111111";
|
||||
|
||||
led0_b_pwm <= not dram_init_done;
|
||||
led0_r_pwm <= dram_init_error;
|
||||
led0_g_pwm <= dram_init_done and not dram_init_error;
|
||||
|
||||
end generate;
|
||||
|
||||
|
||||
-- SD card pmod
|
||||
has_sdcard : if USE_LITESDCARD generate
|
||||
component litesdcard_core port (
|
||||
clk : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
-- wishbone for accessing control registers
|
||||
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
||||
wb_ctrl_cyc : in std_ulogic;
|
||||
wb_ctrl_stb : in std_ulogic;
|
||||
wb_ctrl_ack : out std_ulogic;
|
||||
wb_ctrl_we : in std_ulogic;
|
||||
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
||||
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
||||
wb_ctrl_err : out std_ulogic;
|
||||
-- wishbone for SD card core to use for DMA
|
||||
wb_dma_adr : out std_ulogic_vector(29 downto 0);
|
||||
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
|
||||
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
|
||||
wb_dma_sel : out std_ulogic_vector(3 downto 0);
|
||||
wb_dma_cyc : out std_ulogic;
|
||||
wb_dma_stb : out std_ulogic;
|
||||
wb_dma_ack : in std_ulogic;
|
||||
wb_dma_we : out std_ulogic;
|
||||
wb_dma_cti : out std_ulogic_vector(2 downto 0);
|
||||
wb_dma_bte : out std_ulogic_vector(1 downto 0);
|
||||
wb_dma_err : in std_ulogic;
|
||||
-- connections to SD card
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
irq : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal wb_sdcard_cyc : std_ulogic;
|
||||
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
|
||||
|
||||
begin
|
||||
litesdcard : litesdcard_core
|
||||
port map (
|
||||
clk => system_clk,
|
||||
rst => soc_rst,
|
||||
wb_ctrl_adr => wb_sdcard_adr,
|
||||
wb_ctrl_dat_w => wb_ext_io_in.dat,
|
||||
wb_ctrl_dat_r => wb_sdcard_out.dat,
|
||||
wb_ctrl_sel => wb_ext_io_in.sel,
|
||||
wb_ctrl_cyc => wb_sdcard_cyc,
|
||||
wb_ctrl_stb => wb_ext_io_in.stb,
|
||||
wb_ctrl_ack => wb_sdcard_out.ack,
|
||||
wb_ctrl_we => wb_ext_io_in.we,
|
||||
wb_ctrl_cti => "000",
|
||||
wb_ctrl_bte => "00",
|
||||
wb_ctrl_err => open,
|
||||
wb_dma_adr => wb_sddma_nr.adr,
|
||||
wb_dma_dat_w => wb_sddma_nr.dat,
|
||||
wb_dma_dat_r => wb_sddma_ir.dat,
|
||||
wb_dma_sel => wb_sddma_nr.sel,
|
||||
wb_dma_cyc => wb_sddma_nr.cyc,
|
||||
wb_dma_stb => wb_sddma_nr.stb,
|
||||
wb_dma_ack => wb_sddma_ir.ack,
|
||||
wb_dma_we => wb_sddma_nr.we,
|
||||
wb_dma_cti => open,
|
||||
wb_dma_bte => open,
|
||||
wb_dma_err => '0',
|
||||
sdcard_data => sdcard_data,
|
||||
sdcard_cmd => sdcard_cmd,
|
||||
sdcard_clk => sdcard_clk,
|
||||
sdcard_cd => sdcard_cd,
|
||||
irq => ext_irq_sdcard
|
||||
);
|
||||
|
||||
-- Gate cyc with chip select from SoC
|
||||
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
|
||||
|
||||
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
|
||||
|
||||
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
|
||||
|
||||
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
|
||||
-- non-acknowledged strobes
|
||||
process(system_clk)
|
||||
begin
|
||||
if rising_edge(system_clk) then
|
||||
wb_sddma_out <= wb_sddma_nr;
|
||||
if wb_sddma_stb_sent = '1' or
|
||||
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
|
||||
wb_sddma_out.stb <= '0';
|
||||
end if;
|
||||
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
|
||||
wb_sddma_stb_sent <= '0';
|
||||
elsif wb_sddma_in.stall = '0' then
|
||||
wb_sddma_stb_sent <= wb_sddma_nr.stb;
|
||||
end if;
|
||||
wb_sddma_ir <= wb_sddma_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end generate;
|
||||
|
||||
-- Mux WB response on the IO bus
|
||||
wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else
|
||||
wb_dram_ctrl_out;
|
||||
|
||||
leds_pwm : process(system_clk)
|
||||
begin
|
||||
if rising_edge(system_clk) then
|
||||
pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
|
||||
if pwm_counter(8 downto 4) = "00000" then
|
||||
led0_b <= led0_b_pwm;
|
||||
led0_r <= led0_r_pwm;
|
||||
led0_g <= led0_g_pwm;
|
||||
else
|
||||
led0_b <= '0';
|
||||
led0_r <= '0';
|
||||
led0_g <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture behaviour;
|
||||
@ -1,587 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity toplevel is
|
||||
generic (
|
||||
MEMORY_SIZE : integer := 16384;
|
||||
RAM_INIT_FILE : string := "firmware.hex";
|
||||
RESET_LOW : boolean := true;
|
||||
CLK_FREQUENCY : positive := 100000000;
|
||||
HAS_FPU : boolean := true;
|
||||
HAS_BTC : boolean := true;
|
||||
HAS_SHORT_MULT : boolean := false;
|
||||
USE_LITEDRAM : boolean := false;
|
||||
NO_BRAM : boolean := false;
|
||||
DISABLE_FLATTEN_CORE : boolean := false;
|
||||
SPI_FLASH_OFFSET : integer := 4194304;
|
||||
SPI_FLASH_DEF_CKDV : natural := 1;
|
||||
SPI_FLASH_DEF_QUAD : boolean := true;
|
||||
LOG_LENGTH : natural := 512;
|
||||
USE_LITEETH : boolean := false;
|
||||
UART_IS_16550 : boolean := true;
|
||||
HAS_UART1 : boolean := false;
|
||||
USE_LITESDCARD : boolean := false;
|
||||
HAS_GPIO : boolean := false;
|
||||
NGPIO : natural := 32
|
||||
);
|
||||
port(
|
||||
ext_clk : in std_ulogic;
|
||||
ext_rst_n : in std_ulogic;
|
||||
|
||||
-- UART0 signals:
|
||||
uart_main_tx : out std_ulogic;
|
||||
uart_main_rx : in std_ulogic;
|
||||
|
||||
-- LEDs
|
||||
led0_n : out std_ulogic;
|
||||
led1_n : out std_ulogic;
|
||||
|
||||
-- SPI
|
||||
spi_flash_cs_n : out std_ulogic;
|
||||
spi_flash_mosi : inout std_ulogic;
|
||||
spi_flash_miso : inout std_ulogic;
|
||||
spi_flash_wp_n : inout std_ulogic;
|
||||
spi_flash_hold_n : inout std_ulogic;
|
||||
|
||||
-- Ethernet
|
||||
eth_clocks_tx : in std_ulogic;
|
||||
eth_clocks_gtx : out std_ulogic;
|
||||
eth_clocks_rx : in std_ulogic;
|
||||
eth_rst_n : out std_ulogic;
|
||||
eth_mdio : inout std_ulogic;
|
||||
eth_mdc : out std_ulogic;
|
||||
eth_rx_dv : in std_ulogic;
|
||||
eth_rx_er : in std_ulogic;
|
||||
eth_rx_data : in std_ulogic_vector(7 downto 0);
|
||||
eth_tx_en : out std_ulogic;
|
||||
eth_tx_er : out std_ulogic;
|
||||
eth_tx_data : out std_ulogic_vector(7 downto 0);
|
||||
eth_col : in std_ulogic;
|
||||
eth_crs : in std_ulogic;
|
||||
|
||||
-- SD card
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
|
||||
-- DRAM wires
|
||||
ddram_a : out std_ulogic_vector(13 downto 0);
|
||||
ddram_ba : out std_ulogic_vector(2 downto 0);
|
||||
ddram_ras_n : out std_ulogic;
|
||||
ddram_cas_n : out std_ulogic;
|
||||
ddram_we_n : out std_ulogic;
|
||||
ddram_dm : out std_ulogic_vector(1 downto 0);
|
||||
ddram_dq : inout std_ulogic_vector(15 downto 0);
|
||||
ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
|
||||
ddram_clk_p : out std_ulogic;
|
||||
ddram_clk_n : out std_ulogic;
|
||||
ddram_cke : out std_ulogic;
|
||||
ddram_odt : out std_ulogic;
|
||||
ddram_reset_n : out std_ulogic
|
||||
);
|
||||
end entity toplevel;
|
||||
|
||||
architecture behaviour of toplevel is
|
||||
|
||||
-- Reset signals:
|
||||
signal soc_rst : std_ulogic;
|
||||
signal pll_rst : std_ulogic;
|
||||
|
||||
-- Internal clock signals:
|
||||
signal system_clk : std_ulogic;
|
||||
signal system_clk_locked : std_ulogic;
|
||||
|
||||
-- External IOs from the SoC
|
||||
signal wb_ext_io_in : wb_io_master_out;
|
||||
signal wb_ext_io_out : wb_io_slave_out;
|
||||
signal wb_ext_is_dram_csr : std_ulogic;
|
||||
signal wb_ext_is_dram_init : std_ulogic;
|
||||
signal wb_ext_is_eth : std_ulogic;
|
||||
signal wb_ext_is_sdcard : std_ulogic;
|
||||
|
||||
-- DRAM main data wishbone connection
|
||||
signal wb_dram_in : wishbone_master_out;
|
||||
signal wb_dram_out : wishbone_slave_out;
|
||||
|
||||
-- DRAM control wishbone connection
|
||||
signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
|
||||
-- LiteEth connection
|
||||
signal ext_irq_eth : std_ulogic;
|
||||
signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
|
||||
-- LiteSDCard connection
|
||||
signal ext_irq_sdcard : std_ulogic := '0';
|
||||
signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
|
||||
signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
|
||||
signal wb_sddma_in : wb_io_slave_out;
|
||||
signal wb_sddma_nr : wb_io_master_out;
|
||||
signal wb_sddma_ir : wb_io_slave_out;
|
||||
-- for conversion from non-pipelined wishbone to pipelined
|
||||
signal wb_sddma_stb_sent : std_ulogic;
|
||||
|
||||
-- Control/status
|
||||
signal core_alt_reset : std_ulogic;
|
||||
|
||||
-- SPI flash
|
||||
signal spi_sck : std_ulogic;
|
||||
signal spi_cs_n : std_ulogic;
|
||||
signal spi_sdat_o : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
|
||||
signal spi_sdat_i : std_ulogic_vector(3 downto 0);
|
||||
|
||||
-- ddram clock signals as vectors
|
||||
signal ddram_clk_p_vec : std_ulogic_vector(0 downto 0);
|
||||
signal ddram_clk_n_vec : std_ulogic_vector(0 downto 0);
|
||||
|
||||
-- Fixup various memory sizes based on generics
|
||||
function get_bram_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return 0;
|
||||
else
|
||||
return MEMORY_SIZE;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
function get_payload_size return natural is
|
||||
begin
|
||||
if USE_LITEDRAM and NO_BRAM then
|
||||
return MEMORY_SIZE;
|
||||
else
|
||||
return 0;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
constant BRAM_SIZE : natural := get_bram_size;
|
||||
constant PAYLOAD_SIZE : natural := get_payload_size;
|
||||
begin
|
||||
|
||||
-- Main SoC
|
||||
soc0: entity work.soc
|
||||
generic map(
|
||||
MEMORY_SIZE => BRAM_SIZE,
|
||||
RAM_INIT_FILE => RAM_INIT_FILE,
|
||||
SIM => false,
|
||||
CLK_FREQ => CLK_FREQUENCY,
|
||||
HAS_FPU => HAS_FPU,
|
||||
HAS_BTC => HAS_BTC,
|
||||
HAS_SHORT_MULT => HAS_SHORT_MULT,
|
||||
HAS_DRAM => USE_LITEDRAM,
|
||||
DRAM_SIZE => 256 * 1024 * 1024,
|
||||
DRAM_INIT_SIZE => PAYLOAD_SIZE,
|
||||
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
|
||||
HAS_SPI_FLASH => true,
|
||||
SPI_FLASH_DLINES => 4,
|
||||
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
|
||||
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
|
||||
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
|
||||
LOG_LENGTH => LOG_LENGTH,
|
||||
HAS_LITEETH => USE_LITEETH,
|
||||
UART0_IS_16550 => UART_IS_16550,
|
||||
HAS_UART1 => HAS_UART1,
|
||||
HAS_SD_CARD => USE_LITESDCARD,
|
||||
HAS_GPIO => HAS_GPIO,
|
||||
NGPIO => NGPIO
|
||||
)
|
||||
port map (
|
||||
-- System signals
|
||||
system_clk => system_clk,
|
||||
rst => soc_rst,
|
||||
|
||||
-- UART signals
|
||||
uart0_txd => uart_main_tx,
|
||||
uart0_rxd => uart_main_rx,
|
||||
|
||||
-- SPI signals
|
||||
spi_flash_sck => spi_sck,
|
||||
spi_flash_cs_n => spi_cs_n,
|
||||
spi_flash_sdat_o => spi_sdat_o,
|
||||
spi_flash_sdat_oe => spi_sdat_oe,
|
||||
spi_flash_sdat_i => spi_sdat_i,
|
||||
|
||||
-- External interrupts
|
||||
ext_irq_eth => ext_irq_eth,
|
||||
ext_irq_sdcard => ext_irq_sdcard,
|
||||
|
||||
-- DRAM wishbone
|
||||
wb_dram_in => wb_dram_in,
|
||||
wb_dram_out => wb_dram_out,
|
||||
|
||||
-- IO wishbone
|
||||
wb_ext_io_in => wb_ext_io_in,
|
||||
wb_ext_io_out => wb_ext_io_out,
|
||||
wb_ext_is_dram_csr => wb_ext_is_dram_csr,
|
||||
wb_ext_is_dram_init => wb_ext_is_dram_init,
|
||||
wb_ext_is_eth => wb_ext_is_eth,
|
||||
wb_ext_is_sdcard => wb_ext_is_sdcard,
|
||||
|
||||
-- DMA wishbone
|
||||
wishbone_dma_in => wb_sddma_in,
|
||||
wishbone_dma_out => wb_sddma_out,
|
||||
|
||||
alt_reset => core_alt_reset
|
||||
);
|
||||
|
||||
-- SPI Flash
|
||||
spi_flash_cs_n <= spi_cs_n;
|
||||
spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
|
||||
spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
|
||||
spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
|
||||
spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
|
||||
spi_sdat_i(0) <= spi_flash_mosi;
|
||||
spi_sdat_i(1) <= spi_flash_miso;
|
||||
spi_sdat_i(2) <= spi_flash_wp_n;
|
||||
spi_sdat_i(3) <= spi_flash_hold_n;
|
||||
|
||||
STARTUPE2_INST: STARTUPE2
|
||||
port map (
|
||||
CLK => '0',
|
||||
GSR => '0',
|
||||
GTS => '0',
|
||||
KEYCLEARB => '0',
|
||||
PACK => '0',
|
||||
USRCCLKO => spi_sck,
|
||||
USRCCLKTS => '0',
|
||||
USRDONEO => '1',
|
||||
USRDONETS => '0'
|
||||
);
|
||||
|
||||
nodram: if not USE_LITEDRAM generate
|
||||
signal ddram_clk_dummy : std_ulogic;
|
||||
begin
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked,
|
||||
ext_rst_in => ext_rst_n,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => soc_rst
|
||||
);
|
||||
|
||||
clkgen: entity work.clock_generator
|
||||
generic map(
|
||||
CLK_INPUT_HZ => 50000000,
|
||||
CLK_OUTPUT_HZ => CLK_FREQUENCY
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_rst_in => pll_rst,
|
||||
pll_clk_out => system_clk,
|
||||
pll_locked_out => system_clk_locked
|
||||
);
|
||||
|
||||
core_alt_reset <= '0';
|
||||
|
||||
-- Vivado barfs on those differential signals if left
|
||||
-- unconnected. So instanciate a diff. buffer and feed
|
||||
-- it a constant '0'.
|
||||
dummy_dram_clk: OBUFDS
|
||||
port map (
|
||||
O => ddram_clk_p,
|
||||
OB => ddram_clk_n,
|
||||
I => ddram_clk_dummy
|
||||
);
|
||||
ddram_clk_dummy <= '0';
|
||||
|
||||
end generate;
|
||||
|
||||
has_dram: if USE_LITEDRAM generate
|
||||
signal dram_init_done : std_ulogic;
|
||||
signal dram_init_error : std_ulogic;
|
||||
signal dram_sys_rst : std_ulogic;
|
||||
signal rst_gen_rst : std_ulogic;
|
||||
begin
|
||||
|
||||
-- Eventually dig out the frequency from the generator
|
||||
-- but for now, assert it's 100Mhz
|
||||
assert CLK_FREQUENCY = 100000000;
|
||||
|
||||
reset_controller: entity work.soc_reset
|
||||
generic map(
|
||||
RESET_LOW => RESET_LOW,
|
||||
PLL_RESET_BITS => 18,
|
||||
SOC_RESET_BITS => 1
|
||||
)
|
||||
port map(
|
||||
ext_clk => ext_clk,
|
||||
pll_clk => system_clk,
|
||||
pll_locked_in => system_clk_locked,
|
||||
ext_rst_in => ext_rst_n,
|
||||
pll_rst_out => pll_rst,
|
||||
rst_out => rst_gen_rst
|
||||
);
|
||||
|
||||
-- Generate SoC reset
|
||||
soc_rst_gen: process(system_clk)
|
||||
begin
|
||||
if ext_rst_n = '0' then
|
||||
soc_rst <= '1';
|
||||
elsif rising_edge(system_clk) then
|
||||
soc_rst <= dram_sys_rst or not system_clk_locked;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ddram_clk_p_vec <= (others => ddram_clk_p);
|
||||
ddram_clk_n_vec <= (others => ddram_clk_n);
|
||||
|
||||
dram: entity work.litedram_wrapper
|
||||
generic map(
|
||||
DRAM_ABITS => 24,
|
||||
DRAM_ALINES => 14,
|
||||
DRAM_DLINES => 16,
|
||||
DRAM_CKLINES => 1,
|
||||
DRAM_PORT_WIDTH => 128,
|
||||
PAYLOAD_FILE => RAM_INIT_FILE,
|
||||
PAYLOAD_SIZE => PAYLOAD_SIZE
|
||||
)
|
||||
port map(
|
||||
clk_in => ext_clk,
|
||||
rst => pll_rst,
|
||||
system_clk => system_clk,
|
||||
system_reset => dram_sys_rst,
|
||||
core_alt_reset => core_alt_reset,
|
||||
pll_locked => system_clk_locked,
|
||||
|
||||
wb_in => wb_dram_in,
|
||||
wb_out => wb_dram_out,
|
||||
wb_ctrl_in => wb_ext_io_in,
|
||||
wb_ctrl_out => wb_dram_ctrl_out,
|
||||
wb_ctrl_is_csr => wb_ext_is_dram_csr,
|
||||
wb_ctrl_is_init => wb_ext_is_dram_init,
|
||||
|
||||
init_done => dram_init_done,
|
||||
init_error => dram_init_error,
|
||||
|
||||
ddram_a => ddram_a,
|
||||
ddram_ba => ddram_ba,
|
||||
ddram_ras_n => ddram_ras_n,
|
||||
ddram_cas_n => ddram_cas_n,
|
||||
ddram_we_n => ddram_we_n,
|
||||
ddram_cs_n => open,
|
||||
ddram_dm => ddram_dm,
|
||||
ddram_dq => ddram_dq,
|
||||
ddram_dqs_p => ddram_dqs_p,
|
||||
ddram_dqs_n => ddram_dqs_n,
|
||||
ddram_clk_p => ddram_clk_p_vec,
|
||||
ddram_clk_n => ddram_clk_n_vec,
|
||||
ddram_cke => ddram_cke,
|
||||
ddram_odt => ddram_odt,
|
||||
ddram_reset_n => ddram_reset_n
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
has_liteeth : if USE_LITEETH generate
|
||||
|
||||
component liteeth_core port (
|
||||
sys_clock : in std_ulogic;
|
||||
sys_reset : in std_ulogic;
|
||||
gmii_eth_clocks_tx : in std_ulogic;
|
||||
gmii_eth_clocks_gtx : out std_ulogic;
|
||||
gmii_eth_clocks_rx : in std_ulogic;
|
||||
gmii_eth_rst_n : out std_ulogic;
|
||||
gmii_eth_mdio : inout std_ulogic;
|
||||
gmii_eth_mdc : out std_ulogic;
|
||||
gmii_eth_rx_dv : in std_ulogic;
|
||||
gmii_eth_rx_er : in std_ulogic;
|
||||
gmii_eth_rx_data : in std_ulogic_vector(7 downto 0);
|
||||
gmii_eth_tx_en : out std_ulogic;
|
||||
gmii_eth_tx_er : out std_ulogic;
|
||||
gmii_eth_tx_data : out std_ulogic_vector(7 downto 0);
|
||||
gmii_eth_col : in std_ulogic;
|
||||
gmii_eth_crs : in std_ulogic;
|
||||
wishbone_adr : in std_ulogic_vector(29 downto 0);
|
||||
wishbone_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wishbone_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wishbone_sel : in std_ulogic_vector(3 downto 0);
|
||||
wishbone_cyc : in std_ulogic;
|
||||
wishbone_stb : in std_ulogic;
|
||||
wishbone_ack : out std_ulogic;
|
||||
wishbone_we : in std_ulogic;
|
||||
wishbone_cti : in std_ulogic_vector(2 downto 0);
|
||||
wishbone_bte : in std_ulogic_vector(1 downto 0);
|
||||
wishbone_err : out std_ulogic;
|
||||
interrupt : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal wb_eth_cyc : std_ulogic;
|
||||
signal wb_eth_adr : std_ulogic_vector(29 downto 0);
|
||||
|
||||
-- Change this to use a PLL instead of a BUFR to generate the 25Mhz
|
||||
-- reference clock to the PHY.
|
||||
constant USE_PLL : boolean := false;
|
||||
begin
|
||||
liteeth : liteeth_core
|
||||
port map(
|
||||
sys_clock => system_clk,
|
||||
sys_reset => soc_rst,
|
||||
gmii_eth_clocks_tx => eth_clocks_tx,
|
||||
gmii_eth_clocks_gtx => eth_clocks_gtx,
|
||||
gmii_eth_clocks_rx => eth_clocks_rx,
|
||||
gmii_eth_rst_n => eth_rst_n,
|
||||
gmii_eth_mdio => eth_mdio,
|
||||
gmii_eth_mdc => eth_mdc,
|
||||
gmii_eth_rx_dv => eth_rx_dv,
|
||||
gmii_eth_rx_er => eth_rx_er,
|
||||
gmii_eth_rx_data => eth_rx_data,
|
||||
gmii_eth_tx_en => eth_tx_en,
|
||||
gmii_eth_tx_er => eth_tx_er,
|
||||
gmii_eth_tx_data => eth_tx_data,
|
||||
gmii_eth_col => eth_col,
|
||||
gmii_eth_crs => eth_crs,
|
||||
wishbone_adr => wb_eth_adr,
|
||||
wishbone_dat_w => wb_ext_io_in.dat,
|
||||
wishbone_dat_r => wb_eth_out.dat,
|
||||
wishbone_sel => wb_ext_io_in.sel,
|
||||
wishbone_cyc => wb_eth_cyc,
|
||||
wishbone_stb => wb_ext_io_in.stb,
|
||||
wishbone_ack => wb_eth_out.ack,
|
||||
wishbone_we => wb_ext_io_in.we,
|
||||
wishbone_cti => "000",
|
||||
wishbone_bte => "00",
|
||||
wishbone_err => open,
|
||||
interrupt => ext_irq_eth
|
||||
);
|
||||
|
||||
-- Gate cyc with "chip select" from soc
|
||||
wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
|
||||
|
||||
-- Remove top address bits as liteeth decoder doesn't know about them
|
||||
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
|
||||
|
||||
-- LiteETH isn't pipelined
|
||||
wb_eth_out.stall <= not wb_eth_out.ack;
|
||||
|
||||
end generate;
|
||||
|
||||
no_liteeth : if not USE_LITEETH generate
|
||||
ext_irq_eth <= '0';
|
||||
end generate;
|
||||
|
||||
-- SD card pmod
|
||||
has_sdcard : if USE_LITESDCARD generate
|
||||
component litesdcard_core port (
|
||||
clk : in std_ulogic;
|
||||
rst : in std_ulogic;
|
||||
-- wishbone for accessing control registers
|
||||
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
||||
wb_ctrl_cyc : in std_ulogic;
|
||||
wb_ctrl_stb : in std_ulogic;
|
||||
wb_ctrl_ack : out std_ulogic;
|
||||
wb_ctrl_we : in std_ulogic;
|
||||
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
||||
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
||||
wb_ctrl_err : out std_ulogic;
|
||||
-- wishbone for SD card core to use for DMA
|
||||
wb_dma_adr : out std_ulogic_vector(29 downto 0);
|
||||
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
|
||||
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
|
||||
wb_dma_sel : out std_ulogic_vector(3 downto 0);
|
||||
wb_dma_cyc : out std_ulogic;
|
||||
wb_dma_stb : out std_ulogic;
|
||||
wb_dma_ack : in std_ulogic;
|
||||
wb_dma_we : out std_ulogic;
|
||||
wb_dma_cti : out std_ulogic_vector(2 downto 0);
|
||||
wb_dma_bte : out std_ulogic_vector(1 downto 0);
|
||||
wb_dma_err : in std_ulogic;
|
||||
-- connections to SD card
|
||||
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
||||
sdcard_cmd : inout std_ulogic;
|
||||
sdcard_clk : out std_ulogic;
|
||||
sdcard_cd : in std_ulogic;
|
||||
irq : out std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal wb_sdcard_cyc : std_ulogic;
|
||||
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
|
||||
|
||||
begin
|
||||
litesdcard : litesdcard_core
|
||||
port map (
|
||||
clk => system_clk,
|
||||
rst => soc_rst,
|
||||
wb_ctrl_adr => wb_sdcard_adr,
|
||||
wb_ctrl_dat_w => wb_ext_io_in.dat,
|
||||
wb_ctrl_dat_r => wb_sdcard_out.dat,
|
||||
wb_ctrl_sel => wb_ext_io_in.sel,
|
||||
wb_ctrl_cyc => wb_sdcard_cyc,
|
||||
wb_ctrl_stb => wb_ext_io_in.stb,
|
||||
wb_ctrl_ack => wb_sdcard_out.ack,
|
||||
wb_ctrl_we => wb_ext_io_in.we,
|
||||
wb_ctrl_cti => "000",
|
||||
wb_ctrl_bte => "00",
|
||||
wb_ctrl_err => open,
|
||||
wb_dma_adr => wb_sddma_nr.adr,
|
||||
wb_dma_dat_w => wb_sddma_nr.dat,
|
||||
wb_dma_dat_r => wb_sddma_ir.dat,
|
||||
wb_dma_sel => wb_sddma_nr.sel,
|
||||
wb_dma_cyc => wb_sddma_nr.cyc,
|
||||
wb_dma_stb => wb_sddma_nr.stb,
|
||||
wb_dma_ack => wb_sddma_ir.ack,
|
||||
wb_dma_we => wb_sddma_nr.we,
|
||||
wb_dma_cti => open,
|
||||
wb_dma_bte => open,
|
||||
wb_dma_err => '0',
|
||||
sdcard_data => sdcard_data,
|
||||
sdcard_cmd => sdcard_cmd,
|
||||
sdcard_clk => sdcard_clk,
|
||||
sdcard_cd => sdcard_cd,
|
||||
irq => ext_irq_sdcard
|
||||
);
|
||||
|
||||
-- Gate cyc with chip select from SoC
|
||||
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
|
||||
|
||||
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
|
||||
|
||||
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
|
||||
|
||||
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
|
||||
-- non-acknowledged strobes
|
||||
process(system_clk)
|
||||
begin
|
||||
if rising_edge(system_clk) then
|
||||
wb_sddma_out <= wb_sddma_nr;
|
||||
if wb_sddma_stb_sent = '1' or
|
||||
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
|
||||
wb_sddma_out.stb <= '0';
|
||||
end if;
|
||||
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
|
||||
wb_sddma_stb_sent <= '0';
|
||||
elsif wb_sddma_in.stall = '0' then
|
||||
wb_sddma_stb_sent <= wb_sddma_nr.stb;
|
||||
end if;
|
||||
wb_sddma_ir <= wb_sddma_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end generate;
|
||||
|
||||
-- Mux WB response on the IO bus
|
||||
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
|
||||
wb_sdcard_out when wb_ext_is_sdcard = '1' else
|
||||
wb_dram_ctrl_out;
|
||||
|
||||
led0_n <= system_clk_locked;
|
||||
led1_n <= not soc_rst;
|
||||
|
||||
end architecture behaviour;
|
||||
@ -1,487 +0,0 @@
|
||||
################################################################################
|
||||
# clkin, reset, uart pins...
|
||||
################################################################################
|
||||
|
||||
set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
|
||||
|
||||
set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }];
|
||||
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
|
||||
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
|
||||
|
||||
################################################################################
|
||||
# LEDs
|
||||
################################################################################
|
||||
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led0_n }];
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led1_n }];
|
||||
|
||||
################################################################################
|
||||
# SPI Flash
|
||||
################################################################################ema
|
||||
|
||||
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
|
||||
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
|
||||
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
|
||||
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
|
||||
|
||||
################################################################################
|
||||
# Micro SD
|
||||
################################################################################
|
||||
|
||||
set_property -dict { PACKAGE_PIN M5 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }];
|
||||
set_property -dict { PACKAGE_PIN M7 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }];
|
||||
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }];
|
||||
set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }];
|
||||
set_property -dict { PACKAGE_PIN J8 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }];
|
||||
set_property -dict { PACKAGE_PIN L4 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }];
|
||||
set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }];
|
||||
|
||||
# Put registers into IOBs to improve timing
|
||||
set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}]
|
||||
|
||||
################################################################################
|
||||
# PMOD header J10 (high-speed, no protection resisters)
|
||||
################################################################################
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_1 }];
|
||||
#set_property -dict { PACKAGE_PIN G5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_2 }];
|
||||
#set_property -dict { PACKAGE_PIN G7 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_3 }];
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_4 }];
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_7 }];
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_8 }];
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_9 }];
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { pmod_j10_10 }];
|
||||
|
||||
################################################################################
|
||||
# PMOD header J11 (high-speed, no protection resisters)
|
||||
################################################################################
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_1 }];
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_2 }];
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_3 }];
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_4 }];
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_7 }];
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_8 }];
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_9 }];
|
||||
#set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { pmod_j11_10 }];
|
||||
|
||||
################################################################################
|
||||
# HDR 20X2 connector
|
||||
################################################################################
|
||||
|
||||
## TODO
|
||||
|
||||
################################################################################
|
||||
# Ethernet (generated by LiteX)
|
||||
################################################################################
|
||||
|
||||
# eth_clocks:0.tx
|
||||
set_property LOC M2 [get_ports {eth_clocks_tx}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]
|
||||
|
||||
# eth_clocks:0.gtx
|
||||
set_property LOC U1 [get_ports {eth_clocks_gtx}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_gtx}]
|
||||
|
||||
# eth_clocks:0.rx
|
||||
set_property LOC P4 [get_ports {eth_clocks_rx}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]
|
||||
|
||||
# eth:0.rst_n
|
||||
set_property LOC R1 [get_ports {eth_rst_n}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
|
||||
|
||||
# eth:0.mdio
|
||||
set_property LOC H1 [get_ports {eth_mdio}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]
|
||||
|
||||
# eth:0.mdc
|
||||
set_property LOC H2 [get_ports {eth_mdc}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]
|
||||
|
||||
# eth:0.rx_dv
|
||||
set_property LOC L3 [get_ports {eth_rx_dv}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}]
|
||||
|
||||
# eth:0.rx_er
|
||||
set_property LOC U5 [get_ports {eth_rx_er}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC M4 [get_ports {eth_rx_data[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC N3 [get_ports {eth_rx_data[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC N4 [get_ports {eth_rx_data[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC P3 [get_ports {eth_rx_data[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC R3 [get_ports {eth_rx_data[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[4]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC T3 [get_ports {eth_rx_data[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[5]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC T4 [get_ports {eth_rx_data[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[6]}]
|
||||
|
||||
# eth:0.rx_data
|
||||
set_property LOC T5 [get_ports {eth_rx_data[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[7]}]
|
||||
|
||||
# eth:0.tx_en
|
||||
set_property LOC T2 [get_ports {eth_tx_en}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}]
|
||||
|
||||
# eth:0.tx_er
|
||||
set_property LOC J1 [get_ports {eth_tx_er}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_er}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC R2 [get_ports {eth_tx_data[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC P1 [get_ports {eth_tx_data[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC N2 [get_ports {eth_tx_data[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC N1 [get_ports {eth_tx_data[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC M1 [get_ports {eth_tx_data[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[4]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC L2 [get_ports {eth_tx_data[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[5]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC K2 [get_ports {eth_tx_data[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[6]}]
|
||||
|
||||
# eth:0.tx_data
|
||||
set_property LOC K1 [get_ports {eth_tx_data[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[7]}]
|
||||
|
||||
# eth:0.col
|
||||
set_property LOC U4 [get_ports {eth_col}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}]
|
||||
|
||||
# eth:0.crs
|
||||
set_property LOC U2 [get_ports {eth_crs}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}]
|
||||
|
||||
################################################################################
|
||||
# DRAM (generated by LiteX)
|
||||
################################################################################
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC E17 [get_ports {ddram_a[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC G17 [get_ports {ddram_a[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC F17 [get_ports {ddram_a[2]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC C17 [get_ports {ddram_a[3]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[3]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC G16 [get_ports {ddram_a[4]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[4]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC D16 [get_ports {ddram_a[5]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[5]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC H16 [get_ports {ddram_a[6]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[6]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC E16 [get_ports {ddram_a[7]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[7]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC H14 [get_ports {ddram_a[8]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC F15 [get_ports {ddram_a[9]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC F20 [get_ports {ddram_a[10]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC H15 [get_ports {ddram_a[11]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC C18 [get_ports {ddram_a[12]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
|
||||
|
||||
# ddram:0.a
|
||||
set_property LOC G15 [get_ports {ddram_a[13]}]
|
||||
set_property SLEW FAST [get_ports {ddram_a[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC B17 [get_ports {ddram_ba[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_ba[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC D18 [get_ports {ddram_ba[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_ba[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
|
||||
|
||||
# ddram:0.ba
|
||||
set_property LOC A17 [get_ports {ddram_ba[2]}]
|
||||
set_property SLEW FAST [get_ports {ddram_ba[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
|
||||
|
||||
# ddram:0.ras_n
|
||||
set_property LOC A19 [get_ports {ddram_ras_n}]
|
||||
set_property SLEW FAST [get_ports {ddram_ras_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
|
||||
|
||||
# ddram:0.cas_n
|
||||
set_property LOC B19 [get_ports {ddram_cas_n}]
|
||||
set_property SLEW FAST [get_ports {ddram_cas_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
|
||||
|
||||
# ddram:0.we_n
|
||||
set_property LOC A18 [get_ports {ddram_we_n}]
|
||||
set_property SLEW FAST [get_ports {ddram_we_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC A22 [get_ports {ddram_dm[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dm[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
|
||||
|
||||
# ddram:0.dm
|
||||
set_property LOC C22 [get_ports {ddram_dm[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dm[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC D21 [get_ports {ddram_dq[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[0]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC C21 [get_ports {ddram_dq[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[1]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC B22 [get_ports {ddram_dq[2]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[2]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC B21 [get_ports {ddram_dq[3]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[3]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC D19 [get_ports {ddram_dq[4]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[4]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC E20 [get_ports {ddram_dq[5]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[5]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC C19 [get_ports {ddram_dq[6]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[6]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC D20 [get_ports {ddram_dq[7]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[7]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC C23 [get_ports {ddram_dq[8]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[8]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC D23 [get_ports {ddram_dq[9]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[9]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC B24 [get_ports {ddram_dq[10]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[10]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC B25 [get_ports {ddram_dq[11]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[11]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC C24 [get_ports {ddram_dq[12]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[12]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC C26 [get_ports {ddram_dq[13]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[13]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC A25 [get_ports {ddram_dq[14]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[14]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
|
||||
|
||||
# ddram:0.dq
|
||||
set_property LOC B26 [get_ports {ddram_dq[15]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dq[15]}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC B20 [get_ports {ddram_dqs_p[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
|
||||
|
||||
# ddram:0.dqs_p
|
||||
set_property LOC A23 [get_ports {ddram_dqs_p[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC A20 [get_ports {ddram_dqs_n[0]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
|
||||
|
||||
# ddram:0.dqs_n
|
||||
set_property LOC A24 [get_ports {ddram_dqs_n[1]}]
|
||||
set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
|
||||
|
||||
# ddram:0.clk_p
|
||||
set_property LOC F18 [get_ports {ddram_clk_p}]
|
||||
set_property SLEW FAST [get_ports {ddram_clk_p}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
|
||||
|
||||
# ddram:0.clk_n
|
||||
set_property LOC F19 [get_ports {ddram_clk_n}]
|
||||
set_property SLEW FAST [get_ports {ddram_clk_n}]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
|
||||
|
||||
# ddram:0.cke
|
||||
set_property LOC E18 [get_ports {ddram_cke}]
|
||||
set_property SLEW FAST [get_ports {ddram_cke}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
|
||||
|
||||
# ddram:0.odt
|
||||
set_property LOC G19 [get_ports {ddram_odt}]
|
||||
set_property SLEW FAST [get_ports {ddram_odt}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
|
||||
|
||||
# ddram:0.reset_n
|
||||
set_property LOC H17 [get_ports {ddram_reset_n}]
|
||||
set_property SLEW FAST [get_ports {ddram_reset_n}]
|
||||
set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
|
||||
|
||||
################################################################################
|
||||
# Design constraints and bitsteam attributes
|
||||
################################################################################
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 16]
|
||||
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
################################################################################
|
||||
# Clock constraints
|
||||
################################################################################
|
||||
|
||||
create_clock -name sys_clk_pin -period 20.00 [get_ports { ext_clk }];
|
||||
|
||||
create_clock -name eth_rx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_rx_clk]
|
||||
create_clock -name eth_tx_clk -period 8.0 [get_nets has_liteeth.liteeth/eth_tx_clk]
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets has_liteeth.liteeth/eth_tx_clk]] -asynchronous
|
||||
|
||||
################################################################################
|
||||
# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
|
||||
################################################################################
|
||||
|
||||
set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]
|
||||
Binary file not shown.
Binary file not shown.
@ -1,27 +1,13 @@
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
_start = .;
|
||||
. = 0;
|
||||
.head : {
|
||||
KEEP(*(.head))
|
||||
}
|
||||
}
|
||||
. = 0x1000;
|
||||
.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
|
||||
.text : { *(.text) }
|
||||
. = 0x1800;
|
||||
.data : { *(.data) *(.data.*) *(.got) *(.toc) }
|
||||
. = ALIGN(0x80);
|
||||
__bss_start = .;
|
||||
.bss : {
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.common)
|
||||
*(.bss.*)
|
||||
}
|
||||
. = ALIGN(0x80);
|
||||
__bss_end = .;
|
||||
. = . + 0x2000;
|
||||
__stack_top = .;
|
||||
.data : { *(.data) }
|
||||
.bss : { *(.bss) }
|
||||
}
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
# Matt Johnston 2021
|
||||
# Based on parameters from Greg Davill's Orangecrab-test-sw
|
||||
|
||||
{
|
||||
"cpu": "None", # CPU type (ex vexriscv, serv, None)
|
||||
"device": "LFE5U-85F-8MG285C",
|
||||
"memtype": "DDR3", # DRAM type
|
||||
|
||||
"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
|
||||
"sdram_module_nb": 2, # Number of byte groups
|
||||
"sdram_rank_nb": 1, # Number of ranks
|
||||
"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
|
||||
|
||||
# Electrical ---------------------------------------------------------------
|
||||
"rtt_nom": "disabled", # Nominal termination. ("disabled" from orangecrab)
|
||||
"rtt_wr": "60ohm", # Write termination. (Default)
|
||||
"ron": "34ohm", # Output driver impedance. (Default)
|
||||
|
||||
# Frequency ----------------------------------------------------------------
|
||||
"init_clk_freq": 24e6,
|
||||
"input_clk_freq": 48e6, # Input clock frequency
|
||||
"sys_clk_freq": 48e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
||||
|
||||
# 0 if freq >64e6 else 100. https://github.com/enjoy-digital/litedram/issues/130
|
||||
"cmd_delay": 100,
|
||||
|
||||
# Core ---------------------------------------------------------------------
|
||||
"cmd_buffer_depth": 16, # Depth of the command buffer
|
||||
|
||||
"dm_swap": true,
|
||||
|
||||
# User Ports ---------------------------------------------------------------
|
||||
"user_ports": {
|
||||
"native_0": {
|
||||
"type": "native",
|
||||
"block_until_ready": False,
|
||||
},
|
||||
},
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
{
|
||||
# General ------------------------------------------------------------------
|
||||
"cpu": "None", # CPU type (ex vexriscv, serv, None)
|
||||
"speedgrade": -1, # FPGA speedgrade
|
||||
"memtype": "DDR3", # DRAM type
|
||||
|
||||
# PHY ----------------------------------------------------------------------
|
||||
"cmd_latency": 0, # Command additional latency
|
||||
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
|
||||
"sdram_module_nb": 2, # Number of byte groups
|
||||
"sdram_rank_nb": 1, # Number of ranks
|
||||
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
|
||||
|
||||
# Electrical ---------------------------------------------------------------
|
||||
"rtt_nom": "60ohm", # Nominal termination
|
||||
"rtt_wr": "60ohm", # Write termination
|
||||
"ron": "34ohm", # Output driver impedance
|
||||
|
||||
# Frequency ----------------------------------------------------------------
|
||||
"input_clk_freq": 50e6, # Input clock frequency
|
||||
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
||||
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
|
||||
|
||||
# Core ---------------------------------------------------------------------
|
||||
"cmd_buffer_depth": 16, # Depth of the command buffer
|
||||
|
||||
# User Ports ---------------------------------------------------------------
|
||||
"user_ports": {
|
||||
"native_0": {
|
||||
"type": "native",
|
||||
"block_until_ready": False,
|
||||
},
|
||||
},
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -1,123 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity dram_init_mem is
|
||||
generic (
|
||||
EXTRA_PAYLOAD_FILE : string := "";
|
||||
EXTRA_PAYLOAD_SIZE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
wb_in : in wb_io_master_out;
|
||||
wb_out : out wb_io_slave_out
|
||||
);
|
||||
end entity dram_init_mem;
|
||||
|
||||
architecture rtl of dram_init_mem is
|
||||
|
||||
constant INIT_RAM_SIZE : integer := 24576;
|
||||
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
|
||||
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
|
||||
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
|
||||
constant INIT_RAM_FILE : string := "litedram_core.init";
|
||||
|
||||
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
|
||||
|
||||
-- XXX FIXME: Have a single init function called twice with
|
||||
-- an offset as argument
|
||||
procedure init_load_payload(ram: inout ram_t; filename: string) is
|
||||
file payload_file : text open read_mode is filename;
|
||||
variable ram_line : line;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
begin
|
||||
for i in 0 to RND_PAYLOAD_SIZE-1 loop
|
||||
exit when endfile(payload_file);
|
||||
readline(payload_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
|
||||
ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
assert endfile(payload_file) report "Payload too big !" severity failure;
|
||||
end procedure;
|
||||
|
||||
impure function init_load_ram(name : string) return ram_t is
|
||||
file ram_file : text open read_mode is name;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
variable ram_line : line;
|
||||
begin
|
||||
report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
|
||||
" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
|
||||
report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
|
||||
" bytes using " & integer'image(INIT_RAM_ABITS) &
|
||||
" address bits";
|
||||
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
|
||||
exit when endfile(ram_file);
|
||||
readline(ram_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
temp_ram(i*2) := temp_word(31 downto 0);
|
||||
temp_ram(i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
if RND_PAYLOAD_SIZE /= 0 then
|
||||
init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
|
||||
end if;
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function init_zero return ram_t is
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
begin
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function initialize_ram(filename: string) return ram_t is
|
||||
begin
|
||||
report "Opening file " & filename;
|
||||
if filename'length = 0 then
|
||||
return init_zero;
|
||||
else
|
||||
return init_load_ram(filename);
|
||||
end if;
|
||||
end function;
|
||||
signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of init_ram: signal is "block";
|
||||
|
||||
signal obuf : std_ulogic_vector(31 downto 0);
|
||||
signal oack : std_ulogic;
|
||||
begin
|
||||
|
||||
init_ram_0: process(clk)
|
||||
variable adr : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
oack <= '0';
|
||||
if (wb_in.cyc and wb_in.stb) = '1' then
|
||||
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
|
||||
if wb_in.we = '0' then
|
||||
obuf <= init_ram(adr);
|
||||
else
|
||||
for i in 0 to 3 loop
|
||||
if wb_in.sel(i) = '1' then
|
||||
init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
|
||||
wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
oack <= '1';
|
||||
end if;
|
||||
wb_out.ack <= oack;
|
||||
wb_out.dat <= obuf;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.stall <= '0';
|
||||
|
||||
end architecture rtl;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,123 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
use work.utils.all;
|
||||
|
||||
entity dram_init_mem is
|
||||
generic (
|
||||
EXTRA_PAYLOAD_FILE : string := "";
|
||||
EXTRA_PAYLOAD_SIZE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
wb_in : in wb_io_master_out;
|
||||
wb_out : out wb_io_slave_out
|
||||
);
|
||||
end entity dram_init_mem;
|
||||
|
||||
architecture rtl of dram_init_mem is
|
||||
|
||||
constant INIT_RAM_SIZE : integer := 24576;
|
||||
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
|
||||
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
|
||||
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
|
||||
constant INIT_RAM_FILE : string := "litedram_core.init";
|
||||
|
||||
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
|
||||
|
||||
-- XXX FIXME: Have a single init function called twice with
|
||||
-- an offset as argument
|
||||
procedure init_load_payload(ram: inout ram_t; filename: string) is
|
||||
file payload_file : text open read_mode is filename;
|
||||
variable ram_line : line;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
begin
|
||||
for i in 0 to RND_PAYLOAD_SIZE-1 loop
|
||||
exit when endfile(payload_file);
|
||||
readline(payload_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
|
||||
ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
assert endfile(payload_file) report "Payload too big !" severity failure;
|
||||
end procedure;
|
||||
|
||||
impure function init_load_ram(name : string) return ram_t is
|
||||
file ram_file : text open read_mode is name;
|
||||
variable temp_word : std_logic_vector(63 downto 0);
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
variable ram_line : line;
|
||||
begin
|
||||
report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
|
||||
" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
|
||||
report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
|
||||
" bytes using " & integer'image(INIT_RAM_ABITS) &
|
||||
" address bits";
|
||||
for i in 0 to (INIT_RAM_SIZE/8)-1 loop
|
||||
exit when endfile(ram_file);
|
||||
readline(ram_file, ram_line);
|
||||
hread(ram_line, temp_word);
|
||||
temp_ram(i*2) := temp_word(31 downto 0);
|
||||
temp_ram(i*2+1) := temp_word(63 downto 32);
|
||||
end loop;
|
||||
if RND_PAYLOAD_SIZE /= 0 then
|
||||
init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
|
||||
end if;
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function init_zero return ram_t is
|
||||
variable temp_ram : ram_t := (others => (others => '0'));
|
||||
begin
|
||||
return temp_ram;
|
||||
end function;
|
||||
|
||||
impure function initialize_ram(filename: string) return ram_t is
|
||||
begin
|
||||
report "Opening file " & filename;
|
||||
if filename'length = 0 then
|
||||
return init_zero;
|
||||
else
|
||||
return init_load_ram(filename);
|
||||
end if;
|
||||
end function;
|
||||
signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
|
||||
|
||||
attribute ram_style : string;
|
||||
attribute ram_style of init_ram: signal is "block";
|
||||
|
||||
signal obuf : std_ulogic_vector(31 downto 0);
|
||||
signal oack : std_ulogic;
|
||||
begin
|
||||
|
||||
init_ram_0: process(clk)
|
||||
variable adr : integer;
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
oack <= '0';
|
||||
if (wb_in.cyc and wb_in.stb) = '1' then
|
||||
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
|
||||
if wb_in.we = '0' then
|
||||
obuf <= init_ram(adr);
|
||||
else
|
||||
for i in 0 to 3 loop
|
||||
if wb_in.sel(i) = '1' then
|
||||
init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
|
||||
wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
oack <= '1';
|
||||
end if;
|
||||
wb_out.ack <= oack;
|
||||
wb_out.dat <= obuf;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.stall <= '0';
|
||||
|
||||
end architecture rtl;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -1,17 +0,0 @@
|
||||
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
# PHY ----------------------------------------------------------------------
|
||||
phy: LiteEthPHYGMIIMII
|
||||
vendor: xilinx
|
||||
device: xc7
|
||||
# Core ---------------------------------------------------------------------
|
||||
clk_freq: 100e6
|
||||
core: wishbone
|
||||
endianness: little
|
||||
ntxslots: 2
|
||||
nrxslots: 2
|
||||
|
||||
soc:
|
||||
mem_map:
|
||||
ethmac: 0x00010000
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,6 +0,0 @@
|
||||
interface ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
ftdi_channel 0
|
||||
ftdi_layout_init 0x00e8 0x60eb
|
||||
reset_config none
|
||||
adapter_khz 25000
|
||||
Binary file not shown.
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Reference in New Issue