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  • 471c7e2197 Consolidate VHPI code Anton Blanchard 2020-01-22 14:50:45 +1100
  • 6a9bc46fcb
         Merge pull request #145 from antonblanchard/sim_console-fix Anton Blanchard 2020-01-22 14:48:07 +1100
  • 817315a886 sim_console: Use cfmakeraw() and add option for ctrl-c to exit sim Anton Blanchard 2020-01-22 14:27:40 +1100
  • ace1d32ddb Update Makefile.synth after Paul's patches Anton Blanchard 2020-01-21 14:09:57 +1100
  • f77b31a552
         Merge pull request #134 from paulusmack/master Anton Blanchard 2020-01-21 14:09:36 +1100
  • d876484229
         Merge pull request #142 from antonblanchard/ghdl-synthesis-3 Anton Blanchard 2020-01-21 13:30:13 +1100
  • 4508182fe1
         Merge pull request #144 from antonblanchard/update-README Anton Blanchard 2020-01-21 13:28:43 +1100
  • d1166e9c26
         Merge pull request #143 from antonblanchard/use-docker Anton Blanchard 2020-01-21 13:20:23 +1100
  • 5f2efde644 Add some information about GHDL backend issues Anton Blanchard 2020-01-21 13:13:41 +1100
  • c18830a5e5 Add an option to use Docker Anton Blanchard 2020-01-21 13:03:50 +1100
  • db937403ec Initial support for ghdl synthesis Anton Blanchard 2020-01-18 10:02:07 +1100
  • 21a40c2ba6
         Merge pull request #140 from antonblanchard/rework-makefile Anton Blanchard 2020-01-21 11:41:41 +1100
  • a4dbbfda4a Fix Makefile dependency issue with files in vhdl/* Anton Blanchard 2020-01-20 10:50:45 +1100
  • d1643443d6
         Merge pull request #141 from antonblanchard/update-dependencies.py Anton Blanchard 2020-01-21 11:11:30 +1100
  • d92f3da606 Improve dependencies.py and add a --synth option Anton Blanchard 2020-01-21 10:38:48 +1100
  • ffca138b78
         Merge pull request #136 from antonblanchard/uart-rx-metastability Anton Blanchard 2020-01-19 22:44:32 +1100
  • 61d5e61f09 Add a few FFs on the RX input to avoid metastability issues Anton Blanchard 2020-01-19 14:34:15 +1100
  • 8569ae0ab1
         Merge pull request #139 from antonblanchard/reduce-mem Anton Blanchard 2020-01-19 22:02:56 +1100
  • f5424f8e71 Reduce simulated and default FPGA RAM to 384kB Anton Blanchard 2020-01-19 21:28:32 +1100
  • 488c30fe91 Add log2ceil and use it in bram code Anton Blanchard 2020-01-19 21:18:05 +1100
  • b3dd31a978
         Merge pull request #138 from antonblanchard/micropython-update Anton Blanchard 2020-01-19 21:48:34 +1100
  • d0b5050ca4 Update micropython Anton Blanchard 2020-01-19 20:22:09 +1100
  • 4d3da0c7e6
         Merge pull request #137 from antonblanchard/hello-world Anton Blanchard 2020-01-19 18:40:34 +1100
  • 75f3614776 hello_world updates Anton Blanchard 2020-01-19 16:15:22 +1100
  • 2661b9b985 decode1: Mark subfic as pipelined Paul Mackerras 2020-01-14 23:20:42 +1100
  • e08ca4ab8e countzero: Add a register to help make timing Paul Mackerras 2020-01-14 21:55:33 +1100
  • 5422007f83 Plumb loadstore1 input from execute1 not decode2 Paul Mackerras 2020-01-14 10:28:45 +1100
  • b14d982011 execute: Implement bypass from output of execute1 to input Paul Mackerras 2020-01-13 13:23:42 +1100
  • 0c714f1be6 execute: Move popcnt and prty instructions into the logical unit Paul Mackerras 2020-01-13 18:13:09 +1100
  • d2ca625b3b execute: Do comparisons using the main adder Paul Mackerras 2019-12-13 15:48:54 +1100
  • d956846667 execute1: Move EXTS* instruction back into execute1 Paul Mackerras 2019-12-12 15:25:45 +1100
  • c9a2076dd3 execute1: Remember dest GPR, RC, OE, XER for slow operations Paul Mackerras 2019-12-12 11:21:25 +1100
  • 39d18d2738 Make divider hang off the side of execute1 Paul Mackerras 2019-12-12 08:47:42 +1100
  • 2167186b5f Make multiplier hang off the side of execute1 Paul Mackerras 2019-12-10 20:52:21 +1100
  • 969245e379
         Merge pull request #133 from antonblanchard/ghdl-synth Anton Blanchard 2020-01-11 22:40:44 +1100
  • 729a35967a
         Merge pull request #132 from antonblanchard/bin2hex-move Anton Blanchard 2020-01-11 22:07:42 +1100
  • 9362f2dd10 Move bin2hex.py to scripts/ Anton Blanchard 2020-01-11 21:31:48 +1100
  • f1d0382587 Fix a ghdlsynth issue in fast_spr_num Anton Blanchard 2020-01-11 17:13:23 +1100
  • dcee60a729 Fix a ghdlsynth issue in icache Anton Blanchard 2020-01-11 14:49:06 +1100
  • 3ad3e2abfd Removed unused core_terminated signal Anton Blanchard 2020-01-11 14:43:50 +1100
  • 14c5cf3b83 Fix some ghdlsynth issues with fpga_bram Anton Blanchard 2020-01-11 14:34:25 +1100
  • b0212b0bf9 Fix ghdlsynth issue in register file Anton Blanchard 2020-01-11 14:29:39 +1100
  • f37ef56d79 Remove unused signal Anton Blanchard 2020-01-11 14:28:20 +1100
  • 25968951e4 Fix a ghdysynth inferred latch error in writeback Anton Blanchard 2020-01-11 14:20:35 +1100
  • ad3db18dce Fix a ghdysynth inferred latch error in execute Anton Blanchard 2020-01-11 13:24:14 +1100
  • 0a6fd0adb5
         Merge pull request #131 from antonblanchard/new-tests Anton Blanchard 2020-01-11 12:32:57 +1100
  • cc8a9e7893 Upper 32 bits of XER should read as 0s Anton Blanchard 2020-01-11 12:16:21 +1100
  • 467630573c Dump CTR, LR and CR on sim termination, and update our tests Anton Blanchard 2019-12-11 12:24:46 +1100
  • 115d63eaf3
         Merge pull request #127 from tomtor/CR-PR Anton Blanchard 2020-01-11 10:10:13 +1100
  • 320fc88d56
         Merge pull request #130 from antonblanchard/build-fix Anton Blanchard 2020-01-11 09:02:43 +1100
  • 72aac38581
         Merge pull request #129 from antonblanchard/update-micropython Anton Blanchard 2020-01-11 07:35:37 +1100
  • 1aec1a4b0e Point to upstream micropython Anton Blanchard 2020-01-11 07:20:21 +1100
  • c05441bf47 Implement CRNOR and friends Tom Vijlbrief 2020-01-03 15:25:00 +0100
  • 9a67e3b4fe
         Merge pull request #126 from sharkcz/docs Anton Blanchard 2020-01-04 17:05:37 +1100
  • f552021d19 document packaged fusesoc for Fedora users Dan Horák 2020-01-03 15:09:27 +0100
  • 1c05f330c6 control: Fix build issue with Fedora 31 version of GHDL Anton Blanchard 2019-12-11 12:02:06 +1100
  • 1a826f077b
         Merge pull request #122 from paulusmack/benh-sprs Anton Blanchard 2019-12-09 22:36:29 +1100
  • f5ca58b3c4
         Merge pull request #123 from antonblanchard/spi-conf Anton Blanchard 2019-12-09 20:35:24 +1100
  • 20674e0d65 Add SPI configuration to Xilinx constraint files Anton Blanchard 2019-12-09 16:12:37 +1100
  • 23ade0b1c3 decode2: Minor cleanup Paul Mackerras 2019-12-05 12:42:31 +1100
  • e4f475e17f sprs: Store common SPRs in register file Benjamin Herrenschmidt 2019-10-31 13:48:43 +1100
  • afdd593502 spr: Add translation from SPR to special GPR number Benjamin Herrenschmidt 2019-10-31 12:09:14 +1100
  • 5a0458dec1 divider: Fix overflow calculation Paul Mackerras 2019-12-07 15:26:25 +1100
  • d04887fdcd decode1: Add OE=1 forms of add/sub, mul and div instructions Paul Mackerras 2019-12-06 08:25:28 +1100
  • ec9b27660f execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions Paul Mackerras 2019-12-07 14:31:33 +1100
  • 501b6daf9b Add basic XER support Benjamin Herrenschmidt 2019-10-30 13:53:23 +1100
  • f291efa266 decode1: Mark ALU ops using carry as pipelined Benjamin Herrenschmidt 2019-11-14 15:25:28 +1100
  • 1249a11349 cr_file: Check write_cr_enable Benjamin Herrenschmidt 2019-10-30 13:26:43 +1100
  • ac7df6fc04
         Merge pull request #120 from antonblanchard/spr-decode-cleanup Anton Blanchard 2019-11-18 14:07:16 +1100
  • 726e4db66a
         Merge pull request #119 from antonblanchard/reduce-pipe-depth Anton Blanchard 2019-11-18 14:05:48 +1100
  • 9b1394e236
         Merge pull request #118 from antonblanchard/bus-pipeline Anton Blanchard 2019-11-15 16:02:57 +1100
  • 98bd8b73c0 control: Reduce pipeline depth to 1 Benjamin Herrenschmidt 2019-10-31 19:43:58 +1100
  • 83a8bb0238 spr: Cleanup decoding of SPR numbers Benjamin Herrenschmidt 2019-10-31 11:42:10 +1100
  • cff4b13a9b wb_arbiter: Early master selection Benjamin Herrenschmidt 2019-10-23 15:06:39 +1100
  • bc2acfde2f wb_arbiter: Make arbiter size parametric Benjamin Herrenschmidt 2019-10-23 14:28:12 +1100
  • 472d8f94a2 wb_arbiter: Avoid IDLE cycle when not changing master Benjamin Herrenschmidt 2019-10-23 14:01:48 +1100
  • 336f0e0690 ram: Ack stores early Benjamin Herrenschmidt 2019-10-23 14:00:30 +1100
  • 8e0389b973 ram: Rework main RAM interface Benjamin Herrenschmidt 2019-10-23 12:08:55 +1100
  • 9a63c098a5 Move log2/ispow2 to a utils package Benjamin Herrenschmidt 2019-10-23 10:52:37 +1100
  • 3349bdc798 ram: Add block RAM pipelining Benjamin Herrenschmidt 2019-10-22 16:05:18 +1100
  • 797b1bb045 decode: Reformat decode_types.vhdl Benjamin Herrenschmidt 2019-10-21 22:57:51 +1100
  • d2762e70e5 Add option to not flatten hierarchy Benjamin Herrenschmidt 2019-10-21 15:15:07 +1100
  • 48f260761b writeback: Slightly improve timing Benjamin Herrenschmidt 2019-10-21 15:11:47 +1100
  • 365f60b693 simple_ram: Turn on pipelining Benjamin Herrenschmidt 2019-10-19 10:34:48 +1100
  • c22734d0d9 wb_debug: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:33:31 +1100
  • 3df018cdc0 icache: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:33:04 +1100
  • d363daa692 dcache: Add wishbone pipelining support Benjamin Herrenschmidt 2019-10-19 10:32:46 +1100
  • e638c3e8ae fpga/bram: Generate stall signal Benjamin Herrenschmidt 2019-10-19 21:22:33 +1100
  • 37acb35773 simple_ram: Add pipelining support Benjamin Herrenschmidt 2019-10-19 10:30:39 +1100
  • df1a9237f6 intercon: Generate stall signals for non-pipelined slaves Benjamin Herrenschmidt 2019-10-19 10:27:56 +1100
  • 7a4a9b6377 wb_arbiter: Forward stall signals Benjamin Herrenschmidt 2019-10-19 10:27:02 +1100
  • b1424e859e icache_tb: Initialize stop_mark Benjamin Herrenschmidt 2019-10-19 10:26:09 +1100
  • 79101041d6 wishbone: Add stall signal Benjamin Herrenschmidt 2019-10-17 20:07:18 +1100
  • 559b3bcf2d pp_uart: reformat Benjamin Herrenschmidt 2019-10-19 09:21:42 +1100
  • 9620a76281
         Merge pull request #115 from antonblanchard/reduce-wishbone Anton Blanchard 2019-10-25 17:10:01 +1100
  • 247d7d4aa0
         Merge pull request #113 from mikey/exec-sim-remove Anton Blanchard 2019-10-25 15:52:24 +1100
  • 1b6c246379
         Merge pull request #114 from antonblanchard/dcache Anton Blanchard 2019-10-25 15:49:33 +1100
  • bd4ac06243 Remove SIM generic from execute1 Michael Neuling 2019-10-24 17:07:58 +1100
  • 6dd0b514ac Reduce wishbone address size to 32-bit Benjamin Herrenschmidt 2019-10-17 10:21:41 +1100
  • 1a63c39704 Make it possible to change wishbone address size Benjamin Herrenschmidt 2019-09-25 16:54:25 +1000