A tiny Open POWER ISA softcore written in VHDL 2008

You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Go to file

Anton Blanchard 5e140298a5 Rework decode2 The decode2 stage was spaghetti code and needed cleaning up. Create a series of functions to pull fields from a ppc instruction and also a series of helpers to extract values for the execution units. As suggested by Paul, we should pass all signals to the execution units and only set the valid signal conditionally, which should use less resources. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
fpga	…
hello_world	…
scripts	Remove dynamic ranges from code	5 years ago
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	Rework decode2	5 years ago
README.md	…
common.vhdl	Rework decode2	5 years ago
core.vhdl	…
core_tb.vhdl	…
cr_file.vhdl	…
crhelpers.vhdl	…
decode1.vhdl	…
decode2.vhdl	Rework decode2	5 years ago
decode_types.vhdl	…
execute1.vhdl	Remove dynamic ranges from code	5 years ago
execute2.vhdl	…
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	Remove dynamic ranges from code	5 years ago
insn_helpers.vhdl	Rework decode2	5 years ago
loadstore1.vhdl	…
loadstore2.vhdl	Remove dynamic ranges from code	5 years ago
microwatt.core	Rework decode2	5 years ago
multiply.vhdl	…
multiply_tb.vhdl	…
ppc_fx_insns.vhdl	Remove dynamic ranges from code	5 years ago
register_file.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	…

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

Need to implement a simple non pipelined divide
There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)