matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'ace41e5153'
${ noResults }
microwatt/asic
History
Anton Blanchard ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles 
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 		3 years ago
..
behavioural ASIC: Reduce multiplier from 4 to 2 cycles 3 years ago
cache_ram.vhdl
…
main_bram.vhdl Move register stage back after the RAM 3 years ago
microwatt_asic-verilator.cpp
…
multiply.vhdl ASIC: Reduce multiplier from 4 to 2 cycles 3 years ago
register_file.vhdl
…
top-asic.vhdl Add simplebus 3 years ago