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Anton Blanchard ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles ... Our sky130 gate level multiply/adder now makes timing with a single register stage. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		3 years ago
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behavioural	ASIC: Reduce multiplier from 4 to 2 cycles	3 years ago
cache_ram.vhdl	Add arrays for ASIC flow	3 years ago
main_bram.vhdl	Move register stage back after the RAM	3 years ago
microwatt_asic-verilator.cpp	Add ASIC target	3 years ago
multiply.vhdl	ASIC: Reduce multiplier from 4 to 2 cycles	3 years ago
register_file.vhdl	Add arrays for ASIC flow	3 years ago
top-asic.vhdl	Add simplebus	3 years ago