6d85920068
execute1 no longer needs sim_console
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
d573748da0
Merge pull request #56 from antonblanchard/writeback-fix3
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Remove cycle in writeback
5 years ago
152261fac8
Remove cycle in writeback
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The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
7bb88d5321
Merge pull request #59 from antonblanchard/trap-decode
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Fix make check
5 years ago
f5a5b91736
Merge pull request #58 from antonblanchard/decode2-assert
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Fix spurious outstanding assert
5 years ago
427effdaa9
Fix make check
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We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.
All these trap instructions need to be resolved at completion, not
in execute.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
d813ffb748
Fix spurious outstanding assert
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Check it in the sequential process, not the combinatorial one.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
30aa16d8f3
Merge pull request #57 from antonblanchard/add-nop
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Add a decode for the nop instruction
5 years ago
9867fb6149
Add a decode for the nop instruction
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We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
85062793b1
Merge pull request #55 from antonblanchard/fetch-fix
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Add a default value for RESET_ADDRESS
5 years ago
d52046104f
Add a default value for RESET_ADDRESS
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
71e45a82ee
Merge pull request #51 from antonblanchard/writeback-fix
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Some writeback updates
5 years ago
e69e79d8af
Reformat writeback.vhdl
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
50a361a5dc
Exit if we try to write more than one GPR or CR in a cycle
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
ab34c48392
Merge pull request #50 from antonblanchard/decode1-opt
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No need to gate nia or insn in decode1
5 years ago
acdb2ea157
No need to gate nia or insn in decode1
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
0e6861e5db
Merge pull request #49 from antonblanchard/icache-2
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Add a simple direct mapped icache
5 years ago
89849a6856
Add a simple direct mapped icache
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
6cbf456388
SOC memory wishbone should clear ACK regardless of STB
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The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.
Fixing this improves the situation to one transfer every 2 cycles.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
67446709ca
Merge pull request #48 from antonblanchard/clk_gen_bypass
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Fix clk_gen_bypass
5 years ago
d89a9929fd
Fix clk_gen_bypass
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I broke clk_gen_bypass when updating the SOC reset code.
Fixes 03fd06deaf
5 years ago
80aa781454
Merge pull request #47 from antonblanchard/if-fix
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Explicitly check against '1' in if statements
5 years ago
ca6f84efd6
Merge pull request #46 from antonblanchard/record-fix
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Remove names from end record statements
5 years ago
b9e28598b4
Explicitly check against '1' in if statements
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nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
142a722ce4
Remove names from end record statements
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These are optional, and vhdlpp from iverilog barfs on them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
43f81773b4
Merge pull request #45 from antonblanchard/fixes
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Fix a couple of issues in the recent pipelining merge
5 years ago
7caf71ba71
Fix issue in loadstore1
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We weren't using the register in this stage.
Fixes: 819f820090
5 years ago
95442cd62c
Fix issue in execute2
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We weren't using the register in this stage.
Fixes: c7aa683ba8
5 years ago
1ba84b56dd
Merge pull request #44 from antonblanchard/nia-remove
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Remove nia from loadstore and multiply
5 years ago
1d00c75ecc
Remove nia from loadstore and multiply
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Neither unit needs the NIA, so remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
8b88e26ece
Merge pull request #43 from mikey/trivial
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Remove FIXME comment
5 years ago
Michael Neuling
1e1b799382
Remove FIXME comment
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This was mistakenly left behind in 4d5abfb430
5 years ago
ff1455dea6
Merge pull request #41 from mikey/travis
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Allow a full make check on Travis
5 years ago
2f3ca35a6e
Merge pull request #42 from antonblanchard/fetch-rework-v2
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Fetch rework
5 years ago
4528ef2b43
Reformat core.vhdl
5 years ago
a2df2a10a2
Remove sim console
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We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
68533c4cfb
Reduce multiply to 2 cycles
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We want all non load/store ops to take 2 cycles to make
tracking write back easier.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
9fe8d211eb
Register outputs on writeback
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
c7aa683ba8
Register outputs on execute2
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
819f820090
Register outputs on loadstore1
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
a8f8c54b77
Move debug execute output into decode2
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This covers all units, and we avoid double printing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
92a7152370
Rework pipeline, add stall and flush signals
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This adds stall and flush signals to the pipeline.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling
6b06d5f67d
Allow a full make check on Travis
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Some Travis instances allow more CPU time. On these we can perform the
full 'make check'.
This patch allows this longer `make check`. To enable it you need to
go into your Travis configuration and add a TRAVIS_FULL_CHECK
environment variable.
If you don't add this environment, the shorter make check_light is
still run.
Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
3b32abcb5d
Merge pull request #40 from antonblanchard/makefile-dependencies
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Update Makefile dependencies
5 years ago
b6b2c78163
Update Makefile dependencies
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
d3acb5cce9
Switch soc to use std_ulogic
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
3ac1dbc737
Share soc.vhdl between FPGA and sim
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
d21ef5836d
Pass wishbone record to bram memory module
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(And rename it to mw_soc_memory).
This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
1d66e1f981
Rework wishbone slave address decoding
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Don't make it synchronous, no latches
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
c97b080d8c
Move wishbone arbiter out of the core
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Anton Blanchard
Michael Neuling