ee52fd4d80
Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
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This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.
It's loosely based on the RiscV model (hence the DMI name).
The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.
The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.
This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
1206dfe18c
Use a 3 way WB arbiter and cleanup fpga toplevel
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The 3rd master is currently unused, it will host the WB debug module.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
6571b13308
Merge pull request #66 from antonblanchard/reformat-4
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More reformatting
5 years ago
7e7010c304
Reformat crhelpers, and remove some stale code
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
ae42370d24
Reformat helpers
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
9ff86a62f5
Reformat insn_helpers
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
c5d327cebf
Merge pull request #65 from antonblanchard/loadstore-opt
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A small loadstore optimisation, and some reformatting
5 years ago
687051ecbb
Reformat loadstore1
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
6e442e07a5
Reformat loadstore2
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
e1a71e4545
loads don't do both byte reversal and sign extension
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Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
4df05e0598
Merge pull request #64 from antonblanchard/reformat-3
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Reformat some more files
5 years ago
48f4dcece8
Merge pull request #63 from antonblanchard/multiply-cleanup
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Multiply cleanup
5 years ago
df1165bdfc
Reformat wishbone code
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
06392e7eaa
Reformat glibc_random
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
1d5e8c2eb4
Reformat simple_ram_behavioural
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
fd9e971b2c
Reformat sim_console
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
28e6d343dc
Reformat multiply_tb
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
fc10935797
Reformat execute2
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
4d0afa3a6d
Reformat CR file
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
4d9b2a1165
Reformat register file
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
8dd97fbe7f
Reformat multiply code
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
99dd4de54e
Don't use VHDL 2008 condition operator in multiply
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
550b2b8608
Merge pull request #62 from antonblanchard/byte-reverse-store-opt
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Move byte reversal of stores to first cycle
5 years ago
135805d2ac
Merge pull request #61 from antonblanchard/execute-cleanup
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execute1 no longer needs sim_console
5 years ago
a061924a78
Move byte reversal of stores to first cycle
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We are seeing some timing issues with the second cycle of loadstore,
and we aren't doing much in the first cycle, so move it here.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
6d85920068
execute1 no longer needs sim_console
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
a4c8dd860a
Merge pull request #60 from antonblanchard/testbenches
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Add a few more test benches
5 years ago
1b6eef2a5d
Fix multiply_tb
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
1e3e16e500
Add an icache testbench
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
d573748da0
Merge pull request #56 from antonblanchard/writeback-fix3
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Remove cycle in writeback
5 years ago
152261fac8
Remove cycle in writeback
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The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
7bb88d5321
Merge pull request #59 from antonblanchard/trap-decode
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Fix make check
5 years ago
f5a5b91736
Merge pull request #58 from antonblanchard/decode2-assert
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Fix spurious outstanding assert
5 years ago
427effdaa9
Fix make check
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We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.
All these trap instructions need to be resolved at completion, not
in execute.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
d813ffb748
Fix spurious outstanding assert
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Check it in the sequential process, not the combinatorial one.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
30aa16d8f3
Merge pull request #57 from antonblanchard/add-nop
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Add a decode for the nop instruction
5 years ago
9867fb6149
Add a decode for the nop instruction
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We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
85062793b1
Merge pull request #55 from antonblanchard/fetch-fix
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Add a default value for RESET_ADDRESS
5 years ago
d52046104f
Add a default value for RESET_ADDRESS
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
71e45a82ee
Merge pull request #51 from antonblanchard/writeback-fix
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Some writeback updates
5 years ago
e69e79d8af
Reformat writeback.vhdl
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
50a361a5dc
Exit if we try to write more than one GPR or CR in a cycle
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
ab34c48392
Merge pull request #50 from antonblanchard/decode1-opt
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No need to gate nia or insn in decode1
5 years ago
acdb2ea157
No need to gate nia or insn in decode1
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
0e6861e5db
Merge pull request #49 from antonblanchard/icache-2
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Add a simple direct mapped icache
5 years ago
89849a6856
Add a simple direct mapped icache
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
6cbf456388
SOC memory wishbone should clear ACK regardless of STB
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The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.
Fixing this improves the situation to one transfer every 2 cycles.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
67446709ca
Merge pull request #48 from antonblanchard/clk_gen_bypass
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Fix clk_gen_bypass
5 years ago
d89a9929fd
Fix clk_gen_bypass
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I broke clk_gen_bypass when updating the SOC reset code.
Fixes 03fd06deaf
5 years ago
80aa781454
Merge pull request #47 from antonblanchard/if-fix
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Explicitly check against '1' in if statements
5 years ago
Benjamin Herrenschmidt