* Use bitmasks to describe SPR accesses at the field granularity.
* Use separate checks for each SPR, instead of covering them all at
once. Users may run them in the same batch, and know which SPR passes
or fails its check.
We don't use it currently; we just assume the sync domain is under
reset at the beginning of the BMC.
Also, fix a regression in the cycle counter introduced by 9ea58a47.
* Checks are now split in two modules: checks.cons for consistency
checks, checks.insn for instructions.
* Checks are derived from PowerFVCheck and have a shorthand (e.g.
"insn_b"). PowerFVCheck holds a mapping between its subclasses and
their shorthands.
* Instruction checks definitions have been simplified to one-liners,
and grouped into a single file.
* A Trigger class has been added to define testbench triggers.
- remove check for undefined mnemonics (afaiu, their BO value isn't illegal).
- add check for illegal bcctr/bcctrl forms (with BO(2) = 0).
- fix target offset for branches to LR/CTR/TAR.
- use MSR.SF to check the upper bits of target addresses.
