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@ -77,10 +77,10 @@ begin
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writeback_1: process(all)
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writeback_1: process(all)
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variable v : reg_type;
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variable v : reg_type;
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variable f : WritebackToFetch1Type;
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variable f : WritebackToFetch1Type;
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variable cf: std_ulogic_vector(3 downto 0);
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variable cf: std_ulogic_vector(3 downto 0);
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variable zero : std_ulogic;
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variable zero : std_ulogic;
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variable sign : std_ulogic;
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variable sign : std_ulogic;
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variable scf : std_ulogic_vector(3 downto 0);
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variable scf : std_ulogic_vector(3 downto 0);
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variable vec : integer range 0 to 16#fff#;
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variable vec : integer range 0 to 16#fff#;
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variable srr1 : std_ulogic_vector(15 downto 0);
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variable srr1 : std_ulogic_vector(15 downto 0);
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variable intr : std_ulogic;
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variable intr : std_ulogic;
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@ -228,7 +228,7 @@ begin
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f.mode_32bit := e_in.redir_mode(0);
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f.mode_32bit := e_in.redir_mode(0);
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end if;
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end if;
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f_out <= f;
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f_out <= f;
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flush_out <= f_out.redirect;
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flush_out <= f_out.redirect;
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rin <= v;
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rin <= v;
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