4 Commits (12327034d6308c8ddc2397387e5cfa610e422b55)

Author	SHA1	Message	Date
Olof Kindgren	12327034d6	Add and use plle2 primitive for nexys boards	5 years ago
Olof Kindgren	b9bf19f912	Added synthesis target ... The synth target can be used to analyze the core after synthesis without running P&R. Currently, the only edalize backends that support synthesis without P&R are vivado and icestorm, and icestorm needs yosys built with verific support to parse vhdl. To run synthesis only for a part, run fusesoc run --target=synth --tool=vivado microwatt --part=<part> where part is a valid Xilinx part such as xc7a100tcsg324-1	5 years ago
Olof Kindgren	250d09ed2d	Add Nexys Video support	5 years ago
Olof Kindgren	5e56b14125	Add FuseSoC core description file with Nexys A7 support	5 years ago