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4 Commits (12e8b0952ded227a77c612fd56060e124bc43b08)

Author SHA1 Message Date
Benjamin Herrenschmidt 9961d70dfb Improve PLL/MMCM clocks configuration 
We can now pass both the input clock and target clock frequency
via generics. Add support for both 50Mhz and 100Mhz target freqs
for both cases.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard 142a722ce4 Remove names from end record statements 
These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 03fd06deaf Rework SOC reset 
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Olof Kindgren 12327034d6 Add and use plle2 primitive for nexys boards