microwatt

Author	SHA1	Message	Date
Anton Blanchard	ace41e5153	ASIC: Reduce multiplier from 4 to 2 cycles Our sky130 gate level multiply/adder now makes timing with a single register stage. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	907c833521	Move register stage back after the RAM The 512x64 DFFRAM has quite big hold violations that we can hopefully work around by removing the register stage before the RAM. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	606359cce3	Add simplebus Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	49b332e17f	Hook up JTAG to ASIC top level Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	c2577b5446	Add ASIC target Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	5249d633cf	Move register stage from after RAM to before RAM Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Anton Blanchard	8ecb30da05	Add arrays for ASIC flow Add VHDL wrappers and verilog behaviourals for the cache_ram, register_file and main_bram arrays. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago