matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,100 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '606359cce3'
${ noResults }
Commit Graph

5 Commits (606359cce35f4ba28d58eb53bbde09f3c117c672)

Author SHA1 Message Date
Anton Blanchard 606359cce3 Add simplebus 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 49b332e17f Hook up JTAG to ASIC top level 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard c2577b5446 Add ASIC target 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 5249d633cf Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago