4 Commits (7347786b0859172de64ba7e3aa5abfda74a4c13a)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	5c2fc47e2c	xics: Add simple ICS ... Move the external interrupt generation to a separate module "ICS" (source controller) which a register per source containing currently only the priority control. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	0fa14f6dec	xics: ICP should be big endian ! ... That's how Linux expects it. This also simplifies the register access implementation since the bit fields now align properly regardless of the access size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	573b6b4bc4	soc: Rework interconnect ... This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Michael Neuling	0076f8bf1d	XICS test case ... Checks interrupt masking and priorities. Adds to `make test_xics` which is run in `make check` also. Signed-off-by: Michael Neuling <mikey@neuling.org>	5 years ago