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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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53 Commits (7f44980611c0b0ad06d45732a9f5b2b2179164da)

Author SHA1 Message Date
Benjamin Herrenschmidt 1206dfe18c Use a 3 way WB arbiter and cleanup fpga toplevel 
The 3rd master is currently unused, it will host the WB debug module.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt d3acb5cce9 Switch soc to use std_ulogic 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago