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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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2 Commits (a8d9203c5d9c176a733ea93a8a3d5a376e5071dd)

Author SHA1 Message Date
Paul Mackerras ca4eb46aea Make wishbone addresses be in units of doublewords or words 
This makes the 64-bit wishbone buses have the address expressed in
units of doublewords (64 bits), and similarly for the 32-bit buses the
address is in units of words (32 bits).  This is to comply with the
wishbone spec.  Previously the addresses on the wishbone buses were in
units of bytes regardless of the bus data width, which is not correct
and caused problems with interfacing with externally-generated logic.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Benjamin Herrenschmidt ac81bb17ac litedram: Regenerate 
This regenerate litedram for all targets (genesys2 is new in this
build) using the latest LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago