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fpu-init
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divider-init
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5 Commits (b58ff724f6c87aa57b093d41ab1b951d9edcbf8e)

Author SHA1 Message Date
Paul Mackerras 2843c99a71 MMU: Implement reading of the process table 
This adds the PID register and repurposes SPR 720 as the PRTBL
register, which points to the base of the process table.  There
doesn't seem to be any point to implementing the partition table given
that we don't have hypervisor mode.

The MMU caches entry 0 of the process table internally (in pgtbl3)
plus the entry indexed by the value in the PID register (pgtbl0).
Both caches are invalidated by a tlbie[l] with RIC=2 or by a move to
PRTBL.  The pgtbl0 cache is invalidated by a move to PID.  The dTLB
and iTLB are cleared by a move to either PRTBL or PID.

Which of the two page table root pointers is used (pgtbl0 or pgtbl3)
depends on the MSB of the address being translated.  Since the segment
checking ensures that address(63) = address(62), this is sufficient to
map quadrants 0 and 3.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 6 years ago
Paul Mackerras f3c6119cf6 tests/mmu: Add a test of PTE refetching on permission error 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 6 years ago
Paul Mackerras 8ff8b2f256 tests/mmu: Add a test for dcbz with translation on 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 6 years ago
Paul Mackerras b342312e4e tests: mmu: Add tests for instruction translation 
This adds tests of instruction translation to the mmu test.

This also clears the BSS and improves the linker script.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 6 years ago
Paul Mackerras 882a5a0dc0 tests: Add a test for the MMU radix page table walks 
This adds tests to check that the MMU and dTLB are translating
addresses and checking permissions correctly.

We use a simple 2-level radix tree.  The radix tree maps 2GB of
address space and has a 1024-entry page directory pointing to
512-entry page table pages.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 6 years ago