Commit Graph

840 Commits (bf9a446e3f7f571eef5b67df482f20e2e3582413)
 

Author SHA1 Message Date
Paul Mackerras c180ed0af0 dcache: Output separate done-without-error and error-done signals
This reduces the complexity of the logic in the places where these
signals are used.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 56420e74f3 dcache: Ease timing on calculation of acks remaining
This moves the incrementing or decrementing of r1.acks_pending
to the cycle after a strobe is output or an ack is seen on the
wishbone, and simplifies the logic that determines whether the
cycle is now complete.  This means that the path from seeing
req_op equal to OP_STORE_HIT or OP_STORE_MISS to setting r1.state
and r1.cyc now just involves the stbs_done bit rather than a more
complex calculation involving the possibly incremented r1.acks_pending.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras dc8980d5a5 dcache: Improve timing of valid/done outputs
This makes d_out.valid and m_out.done come directly from registers in
order to improve timing.  The inputs to the registers are set by the
same conditions that cause r1.hit_load_valid, r1.slow_valid,
r1.error_done and r1.stcx_fail to be set.

Note that the STORE_WAIT_ACK state doesn't test r1.mmu_req but assumes
that the request came from loadstore1.  This is because we normally
have r1.full = 0 in this state, which means that r1.mmu_req can
change at any time.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 893d2bc6a2 core: Don't generate logic for log data when LOG_LENGTH = 0
This adds "if LOG_LENGTH > 0 generate" to the places in the core
where log output data is latched, so that when LOG_LENGTH = 0 we
don't create the logic to collect the data which won't be stored.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 03a3a5d326 countzero: Faster algorithm for count leading/trailing zeroes
This uses an algorithm for count leading/trailing zeroes that is
faster on FPGAs, which makes timing easier.  cntlz* and cnttz*
still take two cycles, though.

For count trailing zeroes, we compute x & -x, which for non-zero x
has a single 1 bit in the position of the least-significant 1 bit
in x.  This one-hot representation can then be converted to a bit
number with six 32-input OR gates.  For count leading zeroes, we
simply do a bit-reversal on x and then use the same algorithm.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 1f2058a0ed MMU: Improve timing of done signal back to loadstore1
This makes the l_out.done signal come from a clean latch, which
improves timing.  The cost is that TLB load and invalidation
operations to the dcache now signal done back to loadstore1 one
cycle later than before, but that doesn't seem to affect overall
performance noticeably.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 1be6fbac33 dcache: Remove dependency of r1.wb.adr/dat/sel on req_op
This improves timing by setting r1.wb.{adr,dat,sel} to the next
request when doing a write cycle on the wishbone before we know
whether the next request has a TLB and cache hit or not, i.e.
without depending on req_op.  r1.wb.stb still depends on req_op.

This contains a workaround for what is probably a bug elsewhere,
in that changing r1.wb.sel unconditionally once we see stall=0
from the wishbone causes incorrect behaviour.  Making it
conditional on there being a valid following request appears
to fix the problem.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras c01e1c7b91 dcache: Update TLB PLRU one cycle later
This puts the inputs to the TLB PLRU through a register stage, so
the TLB PLRU update is done in the cycle after the TLB tag
matching rather than the same cycle.  This improves timing.
The PLRU output is only used when writing the TLB in response to
a tlbwe request from the MMU, and that doesn't happen within one
cycle of a virtual-mode load or store, so the fact that the
tlb victim way information is delayed by one cycle doesn't
create any problems.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras b2ba024a48 loadstore1: Eliminate two_dwords variable
The computation of two_dwords from r.second_bytes has shown up as
part of a critical path at times.  Instead we add a 'last_dword'
flag to the reg_stage_t record which tells us more directly
whether a valid flag coming in from dcache means that the
instruction is done, thereby shortening the path to the busy output
back to execute1.

This also simplifies some of the trim_ctl logic.  The two_dwords = 0
case could never have use_second(i) = 1 for any of the bytes being
transferred, so "not use_second(i)" is always 1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 9160e29c56 execute1: Ease timing on redirect_nia
This eliminates a dependency of r.f.redirect_nia on the carry out
from the main adder in the case of a conditional trap instruction.
We can set r.f.redirect_nia unconditionally, even if no interrupt
is generated.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 31587affb3 dcache: Do PLRU update one cycle later
This does the PLRU update based on r1.cache_hit and r1.hit_way rather
than req_op and req_hit_way, which means there is now a register
between the TLB and cache tag lookup and the PLRU update, which should
help with timing.

The PLRU victim selection now becomes valid one cycle later, in the
cycle where r1.write_tag = 1.  We now have replace_way coming from
the PLRU when r1.write_tag = 1 and from r1.store_way at other times,
and we use that instead of r1.store_way in situations where we need
it to be valid in the first cycle of the RELOAD_WAIT_ACK state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 144d8e3c61 icache: Do PLRU update one cycle later
This does the PLRU update based on r.hit_valid and r.hit_way rather
than req_is_hit and req_hit_way, which means there is now a register
between the TLB and cache tag lookup and the PLRU update, which
should help with timing.

As a result, the PLRU victim way selection becomes valid one cycle
later, in the cycle when r.state = CLR_TAG.  So we have to use the
PLRU output directly in the CLR_TAG state and r.store_way in the
WAIT_ACK state.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling 57ad7effed
Merge pull request #232 from gromero/for-anton
Enhance hello_world
4 years ago
Gustavo Romero dee71e8f01 Enhance hello_world
This commit enhances hello_world.bin output by printing
a ASCII lightbulb, which turns out to be Microwatt's logo,
instead of simply a "Hello World" text message.

Signed-off-by: Gustavo Romero <gustavo.romero@protonmail.com>
4 years ago
Michael Neuling 2081bdaa27
Merge pull request #228 from ozbenh/misc
Misc nexys video fixes
4 years ago
Michael Neuling 4d7143bf6b
Merge pull request #222 from iamjpn/master
core: Implement PVR register
4 years ago
Jordan Niethe 737ebd92f5 tests: Add tests for the PVR
The PVR is a privileged read-only SPR. Test reading and writing in both
supervisor and problem state. In supervisor state reading returns
microwatt's assigned PVR number and writing is a noop. In problem state
both reading and writing cause privileged instruction interrupts.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
4 years ago
Benjamin Herrenschmidt ac81bb17ac litedram: Regenerate
This regenerate litedram for all targets (genesys2 is new in this
build) using the latest LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 079af6443e litedram: Update generator to work with latest LiteX
Some changes in LiteX broke us. Adapt the build system and
increase the init RAM size to 24KB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt cc35c49928 litedram: Add generator for Genesys2
(Not yet generated)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour
litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 02abb135a8 litedram: l2: Add support for more geometries
Make the DRAM data lines and user port width configurable, also
don't hard wire dependency on the wishbone data width.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 1441b2a859 litedram: l2: Latency improvements
This implements in the L2 cache the feature already in the L1s
allowing a request to be completed before the end of a refill
using partial line valid bits, and starting a refill from the
row of the first miss on that line instead of the beginning of
the line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt b0241d9f2d corefile/nexys_video: Parameter fixes
This fixes up a few issues with parameters:

Only arty has "has_uart1" since we haven't added plumbing for a second UART
anywhere else. Also "uart_is_16550" was mixing on one of the nexys_video
targets, and nexys_video toplevel was missing LOG_LENGTH.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt a5fa92f71b fpga: nexys-video: Wire up core_alt_reset
It looks like we left it dangling

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 5449d842dd nexys_video: Fix nexys-video build
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 3c2739e10a spi: Send dummy clocks at boot
When using an FPGA which routes the SPI clock via STARTUPE2 as is
done on the Nexys Video (or optionally on Arty), the HW needs at
least 3 beats of that clock to complete the switch from the internal
config clock to the one we provide.

This works around it by having the SPI controller send 8 dummy
clocks at boot time with CS held high.

Without this, flash identification will fail those boards

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras bf36ea365b
Merge pull request #223 from mikey/ecp5
Make ECP5 devices work and add github artifacts
4 years ago
Michael Neuling b3b28044f8 Create github artifacts for ECP5 devices
ECP5 eval board (tested and working) and Orange Crap (untested)

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 5aaa63ee3b Add PLL for ECP5 device
Means we can synthesize at 40Mhz (where we currently make timing) and
our UART still works at 115200 baud.

Tested working hello world unmodified with ECP5 eval board. Orange
Crab is updated but is untested.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Anton Blanchard 4e977bf8a9
Merge pull request #220 from mikey/ghdl-makefile
Use $(GHDL) rather than ghdl in Makefile
4 years ago
Anton Blanchard 65fc34cf6e
Merge pull request #209 from mikey/yosys
Make yosys/nextpnr work and add to CI
4 years ago
Jordan Niethe 17fc77cef2 core: Implement PVR register
Microwatt has been allocated a PVR version of 0x0063. Implement a PVR
with this value.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
4 years ago
Michael Neuling 1697f8a08f Use $(GHDL) rather than ghdl in Makefile
Suggestion from @eine in PR #219.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 8bfc6a21b9 Add yosys/nextpnr ecp5 and verilog build to CI
This works now, so let's make sure it continues to.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 10a1a86ba0 Add FPGA_TARGET=ECP5-EVN make option for synthesis build
This allows these targets
  FPGA_TARGET=ORANGE-CRAB make microwatt.bit
  FPGA_TARGET=ECP5-EVN make microwatt.bit
Default is ORANGE-CRAB as before

ECP5-EVN is tested on real hardware. The console only works at 38400 so
needs this in console.c and a recompile of hello_world to work:

  -#define UART_FREQ 115200
  +#define UART_FREQ 38400

With this 'FPGA_TARGET=ECP5-EVN make prog' works on the ECP5 dev board.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ef0dcf3bc6 Add SYNTH_ECP5_FLAGS option for building
This is useful to specify "-noflatten" which helps CI stay under 8GB
limit.

Normally the AUTONAME stage of yosys will take around 10GB if
operating on the whole design. With -noflatten, AUTONAME occurs only
per VHDL entity, so only consumes around 3GB of memory. This gets us
under the limitations on github actions.

More discussion here:
  https://github.com/antonblanchard/microwatt/pull/209#issuecomment-652186078

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 45fd2354f2 Add ram file to synthesis build dependencies
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 7347786b08 Add uart16550 files to yosys/nextpnr build
These are verilog so need passed to yosys differently than the VHDL
files.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling aae45583d7 Add uart16550 files from fusesoc
These are needed for synthesis that doesn't use fusesoc natively.

These were pulled in via 'fusesoc fetch ::uart16550:1.5.5-r1'

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3f6d48f2fc Build to tmp file so nextpnr errors don't confuse make
nextpnr will leave an output file around even when it errors out, so
build to a tmp file and move it when we succeed so we don't confuse
make.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3e0ac8c94c Fix building with yosys/nextpnr
Add --no-formal so that asserts are removed by yosys as nextpnr
doesn't like them.

This was suggested by @tgingold here:
  https://github.com/YosysHQ/yosys/issues/2068#issuecomment-644545863

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 3460afb557 Add yosys builds files to gitignore
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling b1c260599f Send line feed if we get a carriage return in hello world.
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling ce0205b262
Merge pull request #216 from paulusmack/cfar
Timing and speed improvements, implement CFAR register
4 years ago
Paul Mackerras 419c9a68e8
Merge pull request #206 from Jbalkind/icachecleanup
Icache constants cleanup
4 years ago
Paul Mackerras 74062195ca execute1: Do forwarding of the CR result to the next instruction
This adds a path to allow the CR result of one instruction to be
forwarded to the next instruction, so that sequences such as
cmp; bc can avoid having a 1-cycle bubble.

Forwarding is not available for dot-form (Rc=1) instructions,
since the CR result for them is calculated in writeback.  The
decode.output_cr field is used to identify those instructions
that compute the CR result in execute1.

For some reason, the multiply instructions incorrectly had
output_cr = 1 in the decode tables.  This fixes that.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 0f0573903b execute1: Add latch to redirect path
This latches the redirect signal inside execute1, so that it is sent
a cycle later to fetch1 (and to decode/icache as flush).  This breaks
a long combinatorial chain from the branch and interrupt detection
in execute1 through the redirect/flush signals all the way back to
fetch1, icache and decode.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras 9b40b5a77b logical: Only do output inversion for OP_AND, OP_OR and OP_XOR
It's not needed for the other ops (popcnt, parity, etc.) and the
logical unit shows up as a critical path from time to time.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras c2da82764f core: Implement CFAR register
This implements the CFAR SPR as a slow SPR stored in 'ctrl'.  Taken
branches and rfid update it to the address of the branch or rfid
instruction.

To simplify the logic, this makes rfid use the branch logic to
generate its redirect (requiring SRR0 to come in to execute1 on
the B input and SRR1 on the A input), and the masking of the bottom
2 bits of NIA is moved to fetch1.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago