matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,039 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'ceb15d3ca8'
${ noResults }
Commit Graph

1039 Commits (ceb15d3ca8c93b1d90019400d62d4911073d14a0)
 

Author SHA1 Message Date
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt d21ef5836d Pass wishbone record to bram memory module 
(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 1d66e1f981 Rework wishbone slave address decoding 
Don't make it synchronous, no latches

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt c97b080d8c Move wishbone arbiter out of the core 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 310a56c076 Re-indent and reformat soc.vhdl 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc 
This will be useful when we start needing different toplevels for
different boards.

We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 5ee86e7621
Merge pull request #39 from antonblanchard/no-x-state 
Don't send out X state from the memory behavioural
 5 years ago
Anton Blanchard dce2e06f4c Don't send out X state from the memory behavioural 
Just send out all 1s.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard c3a5782bf4
Merge pull request #36 from mikey/gitignore 
Add new files to git ignore
 5 years ago
Anton Blanchard 419b95a447
Merge pull request #38 from antonblanchard/multiply-warn 
Quieten multiply warning
 5 years ago
Anton Blanchard a22afbdb5b Quieten multiply warning 
We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Michael Neuling 5ae92a721f Add new files to git ignore 
Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Anton Blanchard d79c994158
Merge pull request #35 from antonblanchard/multiply-opt 
Simplify multiply
 5 years ago
Anton Blanchard 18b9b39a2c Simplify multiply 
No need to gate everything with the valid bit.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 47f39440f2
Merge pull request #34 from antonblanchard/decode-table 
Decode table
 5 years ago
Anton Blanchard 9687034d78 Add a decode bit to mark an instruction as single through the pipeline 
This is used by the pipelining patches. Mark everyone as single through
the pipeline to start.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt b0ade2857f decode1 array fix header 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard a9065796ad
Merge pull request #33 from antonblanchard/cr-fix 
Fix CR forwarding
 5 years ago
Anton Blanchard e0dfb3dce1
Merge pull request #32 from antonblanchard/register-file-forwarding 
Add forwarding in the register file
 5 years ago
Benjamin Herrenschmidt 8bfd6e5eae Use simulated UART in core test bench 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 1b9c6f4647 Make sim poll non-blocking 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 48b689b665 Add simulated UART design 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 9cbdecb561 Fix CR forwarding 
We weren't actually forwarding writes in the same cycle. Not a
problem right now, but noticed when testing the pipelining series.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 79a14c8e37 Add forwarding in the register file 
We need this for the upcoming pipelining patches.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 2241b71674
Merge pull request #31 from antonblanchard/no-second-write-port-2 
More second write port removal
 5 years ago
Anton Blanchard 045a00c5d7
Merge pull request #30 from antonblanchard/writeback-assert 
Add some assertions to writeback
 5 years ago
Anton Blanchard 31a6fb6ef5 More second write port removal 
I missed the register file updates for the second write port
removal.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard fa04936c92 Add some assertions to writeback 
We want to make sure we never complete more than one
instruction per cycle, or write back more than one GPR
or CR per cycle.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 4c872619b3
Merge pull request #29 from antonblanchard/no-second-write-port 
Remove second write port
 5 years ago
Anton Blanchard f384f504a1
Merge pull request #28 from antonblanchard/loadstore-cleanup 
Remove some more loadstore debug
 5 years ago
Anton Blanchard fb4cad6eaf Remove second write port 
We only need two write ports for load with update instructions.
Having two write ports just for this instruction is expensive.

For now we will force them to be the only instruction in the
pipeline, and take two cycles of writeback.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard aee5fded44 Remove some more loadstore debug 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard ff9070d727
Merge pull request #27 from antonblanchard/fix-cr 
Fix issues with CR rework
 5 years ago
Anton Blanchard 0254e40685 Fix issues with CR rework 
It simulated fine, but didn't synthesize. Fix some obvious issues
to get us going again.

Fixes: 9fbaea6f08 ("Rework CR file and add forwarding")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard b8d93728d7
Merge pull request #26 from antonblanchard/silence-loadstore-debug 
Silence some loadstore related debug
 5 years ago
Anton Blanchard a1ab1d3e56
Merge pull request #25 from antonblanchard/register_file_printing 
Clean up register read debug output
 5 years ago
Anton Blanchard a5d31bb554
Merge pull request #24 from antonblanchard/cr_file_cleanup 
Rework CR file and add forwarding
 5 years ago
Anton Blanchard 5d82af5204 Silence some loadstore related debug 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 04eb9583e6 Clean up register read debug output 
Right now we continually print all 3 possible GPRs an instruction
may be using. Add signals so we only print GPRs when they are
actually read. This should hopefully optimise away when synthesized.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 9fbaea6f08 Rework CR file and add forwarding 
Handle the CR as a single field with per nibble enables. Forward any
writes in the same cycle.

If this proves to be an issue for timing, we may want to revisit
this in the future. For now, it keeps things simple.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 7c2a2b7414
Merge pull request #19 from antonblanchard/cmod-a7 
Cmod A7-35 support
 5 years ago
Anton Blanchard 270d7b1b9a Cmod A7-35 support 
This adds support for the Digilane Cmod A7-35.

I had to use the MMCM because the clock (12 MHz) is below the PLL
minimum of 19 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 14da542d4a
Merge pull request #20 from antonblanchard/reset-rework2 
Rework reset code
 5 years ago
Anton Blanchard 0832fed06c
Merge pull request #22 from antonblanchard/store-fix 
Stores need to wait for wishbone write ack
 5 years ago
Anton Blanchard 021d427d3f Stores need to wait for wishbone write ack 
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard c64bf23c1a
Merge pull request #21 from antonblanchard/xdc-update 
Add CONFIG_VOLTAGE and CFGBVS entries
 5 years ago
Anton Blanchard 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries 
Remove a couple of warnings from Vivado.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 03fd06deaf Rework SOC reset 
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard a53ad60014 Rename a few reset signals 
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard e39400681b
Merge pull request #18 from mikey/verific 
Fix verific script with new VHDL files
 5 years ago