matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,050 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'd794cc70b1'
${ noResults }
Commit Graph

4 Commits (d794cc70b13f7538a98beffee3069db4aa9ea758)

Author SHA1 Message Date
Matt Johnston 5a3cdc8b22 litedram: disable block_until_ready, regenerate 
Recent litedram gets stuck at memtest unless block_until_ready=False.
(discussion in https://github.com/enjoy-digital/litedram/pull/292)

This change regenerates with latest litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago
Anton Blanchard ac546a3024 litedram: Update yaml files 
Update the litedram yaml files based on latest upstream.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Boris Shingarov 679c547e5f fpga: Add support for Genesys2 
Signed-off-by: Boris Shingarov <shingarov@labware.com>
 4 years ago
Benjamin Herrenschmidt cc35c49928 litedram: Add generator for Genesys2 
(Not yet generated)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 4 years ago