56 Commits (fc4e13ae67ef7d49480cd0095850814c0d040583)

Author	SHA1	Message	Date
Anton Blanchard	5379b805ec	Arty A7 reset pin is C2 ... Use C2 for reset, and fix up a few whitespace issues. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
riktw	4ebd6fc1f7	Added support for building for Arty A7 boards	5 years ago
Olof Kindgren	12327034d6	Add and use plle2 primitive for nexys boards	5 years ago
Olof Kindgren	b9bf19f912	Added synthesis target ... The synth target can be used to analyze the core after synthesis without running P&R. Currently, the only edalize backends that support synthesis without P&R are vivado and icestorm, and icestorm needs yosys built with verific support to parse vhdl. To run synthesis only for a part, run fusesoc run --target=synth --tool=vivado microwatt --part=<part> where part is a valid Xilinx part such as xc7a100tcsg324-1	5 years ago
Olof Kindgren	250d09ed2d	Add Nexys Video support	5 years ago
Olof Kindgren	5e56b14125	Add FuseSoC core description file with Nexys A7 support	5 years ago