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Commit Graph

  • 7caf71ba71 Fix issue in loadstore1 Anton Blanchard 2019-09-11 22:40:53 +1000
  • 95442cd62c Fix issue in execute2 Anton Blanchard 2019-09-11 22:39:30 +1000
  • 1ba84b56dd
         Merge pull request #44 from antonblanchard/nia-remove Anton Blanchard 2019-09-11 21:58:01 +1000
  • 1d00c75ecc Remove nia from loadstore and multiply Anton Blanchard 2019-09-11 21:42:37 +1000
  • 8b88e26ece
         Merge pull request #43 from mikey/trivial Anton Blanchard 2019-09-11 21:42:00 +1000
  • 1e1b799382 Remove FIXME comment Michael Neuling 2019-09-11 16:50:57 +1000
  • ff1455dea6
         Merge pull request #41 from mikey/travis Anton Blanchard 2019-09-11 16:05:05 +1000
  • 2f3ca35a6e
         Merge pull request #42 from antonblanchard/fetch-rework-v2 Anton Blanchard 2019-09-11 16:04:10 +1000
  • 4528ef2b43 Reformat core.vhdl Anton Blanchard 2019-09-11 07:55:35 +1000
  • a2df2a10a2 Remove sim console Anton Blanchard 2019-09-11 07:16:56 +1000
  • 68533c4cfb Reduce multiply to 2 cycles Anton Blanchard 2019-09-10 16:22:58 +1000
  • 9fe8d211eb Register outputs on writeback Anton Blanchard 2019-09-10 16:04:39 +1000
  • c7aa683ba8 Register outputs on execute2 Anton Blanchard 2019-09-10 15:40:20 +1000
  • 819f820090 Register outputs on loadstore1 Anton Blanchard 2019-09-10 15:39:50 +1000
  • a8f8c54b77 Move debug execute output into decode2 Anton Blanchard 2019-09-10 15:02:18 +1000
  • 92a7152370 Rework pipeline, add stall and flush signals Anton Blanchard 2019-09-04 09:36:30 +1000
  • 6b06d5f67d Allow a full make check on Travis Michael Neuling 2019-09-11 10:18:19 +1000
  • 3b32abcb5d
         Merge pull request #40 from antonblanchard/makefile-dependencies Anton Blanchard 2019-09-11 07:48:19 +1000
  • b6b2c78163 Update Makefile dependencies Anton Blanchard 2019-09-11 07:32:00 +1000
  • d3acb5cce9 Switch soc to use std_ulogic Benjamin Herrenschmidt 2019-09-10 16:59:10 +0100
  • 3ac1dbc737 Share soc.vhdl between FPGA and sim Benjamin Herrenschmidt 2019-09-10 16:40:11 +0100
  • d21ef5836d Pass wishbone record to bram memory module Benjamin Herrenschmidt 2019-09-10 16:39:52 +0100
  • 1d66e1f981 Rework wishbone slave address decoding Benjamin Herrenschmidt 2019-09-10 14:52:23 +0100
  • c97b080d8c Move wishbone arbiter out of the core Benjamin Herrenschmidt 2019-08-31 18:54:58 +1000
  • 310a56c076 Re-indent and reformat soc.vhdl Benjamin Herrenschmidt 2019-09-10 13:01:17 +0100
  • a69a93b466 Split FPGA toplevel from soc Benjamin Herrenschmidt 2019-09-10 12:45:33 +0100
  • 5ee86e7621
         Merge pull request #39 from antonblanchard/no-x-state Anton Blanchard 2019-09-10 17:07:09 +1000
  • dce2e06f4c Don't send out X state from the memory behavioural Anton Blanchard 2019-09-10 16:46:41 +1000
  • c3a5782bf4
         Merge pull request #36 from mikey/gitignore Anton Blanchard 2019-09-10 16:31:37 +1000
  • 419b95a447
         Merge pull request #38 from antonblanchard/multiply-warn Anton Blanchard 2019-09-10 16:31:08 +1000
  • a22afbdb5b Quieten multiply warning Anton Blanchard 2019-09-10 15:31:54 +1000
  • 5ae92a721f Add new files to git ignore Michael Neuling 2019-09-10 15:00:35 +1000
  • d79c994158
         Merge pull request #35 from antonblanchard/multiply-opt Anton Blanchard 2019-09-10 09:14:31 +1000
  • 18b9b39a2c Simplify multiply Anton Blanchard 2019-09-08 11:11:15 +1000
  • 47f39440f2
         Merge pull request #34 from antonblanchard/decode-table Anton Blanchard 2019-09-10 08:09:48 +1000
  • 9687034d78 Add a decode bit to mark an instruction as single through the pipeline Anton Blanchard 2019-09-02 16:11:31 +1000
  • b0ade2857f decode1 array fix header Benjamin Herrenschmidt 2019-09-03 08:44:01 +1000
  • a9065796ad
         Merge pull request #33 from antonblanchard/cr-fix Anton Blanchard 2019-09-09 22:44:34 +1000
  • e0dfb3dce1
         Merge pull request #32 from antonblanchard/register-file-forwarding Anton Blanchard 2019-09-09 22:21:30 +1000
  • 8bfd6e5eae Use simulated UART in core test bench Benjamin Herrenschmidt 2019-08-28 00:09:45 +1000
  • 1b9c6f4647 Make sim poll non-blocking Benjamin Herrenschmidt 2019-08-28 00:09:24 +1000
  • 48b689b665 Add simulated UART design Benjamin Herrenschmidt 2019-08-28 00:08:54 +1000
  • 9cbdecb561 Fix CR forwarding Anton Blanchard 2019-09-09 22:16:11 +1000
  • 79a14c8e37 Add forwarding in the register file Anton Blanchard 2019-09-09 16:36:47 +1000
  • 2241b71674
         Merge pull request #31 from antonblanchard/no-second-write-port-2 Anton Blanchard 2019-09-09 16:12:59 +1000
  • 045a00c5d7
         Merge pull request #30 from antonblanchard/writeback-assert Anton Blanchard 2019-09-09 16:12:39 +1000
  • 31a6fb6ef5 More second write port removal Anton Blanchard 2019-09-09 16:00:49 +1000
  • fa04936c92 Add some assertions to writeback Anton Blanchard 2019-09-09 15:54:09 +1000
  • 4c872619b3
         Merge pull request #29 from antonblanchard/no-second-write-port Anton Blanchard 2019-09-09 15:51:34 +1000
  • f384f504a1
         Merge pull request #28 from antonblanchard/loadstore-cleanup Anton Blanchard 2019-09-09 15:50:46 +1000
  • fb4cad6eaf Remove second write port Anton Blanchard 2019-09-09 15:18:09 +1000
  • aee5fded44 Remove some more loadstore debug Anton Blanchard 2019-09-09 15:03:06 +1000
  • ff9070d727
         Merge pull request #27 from antonblanchard/fix-cr Anton Blanchard 2019-09-09 13:35:12 +1000
  • 0254e40685 Fix issues with CR rework Anton Blanchard 2019-09-09 13:03:27 +1000
  • b8d93728d7
         Merge pull request #26 from antonblanchard/silence-loadstore-debug Anton Blanchard 2019-09-09 11:42:55 +1000
  • a1ab1d3e56
         Merge pull request #25 from antonblanchard/register_file_printing Anton Blanchard 2019-09-09 11:42:41 +1000
  • a5d31bb554
         Merge pull request #24 from antonblanchard/cr_file_cleanup Anton Blanchard 2019-09-09 11:41:44 +1000
  • 5d82af5204 Silence some loadstore related debug Anton Blanchard 2019-09-09 11:23:29 +1000
  • 04eb9583e6 Clean up register read debug output Anton Blanchard 2019-09-09 11:18:26 +1000
  • 9fbaea6f08 Rework CR file and add forwarding Anton Blanchard 2019-09-09 09:32:08 +1000
  • 7c2a2b7414
         Merge pull request #19 from antonblanchard/cmod-a7 Anton Blanchard 2019-09-08 18:04:38 +1000
  • 270d7b1b9a Cmod A7-35 support Anton Blanchard 2019-09-06 16:24:16 +1000
  • 14da542d4a
         Merge pull request #20 from antonblanchard/reset-rework2 Anton Blanchard 2019-09-08 16:34:10 +1000
  • 0832fed06c
         Merge pull request #22 from antonblanchard/store-fix Anton Blanchard 2019-09-08 16:23:54 +1000
  • 021d427d3f Stores need to wait for wishbone write ack Anton Blanchard 2019-09-08 16:00:36 +1000
  • c64bf23c1a
         Merge pull request #21 from antonblanchard/xdc-update Anton Blanchard 2019-09-08 10:19:29 +1000
  • 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries Anton Blanchard 2019-09-08 09:49:39 +1000
  • 03fd06deaf Rework SOC reset Anton Blanchard 2019-09-07 21:28:21 +1000
  • a53ad60014 Rename a few reset signals Anton Blanchard 2019-09-07 21:08:02 +1000
  • e39400681b
         Merge pull request #18 from mikey/verific Anton Blanchard 2019-09-06 20:54:50 +1000
  • 83d773090e Fix verific script with new VHDL files Michael Neuling 2019-09-06 15:05:01 +1000
  • a15eb4e28d
         Merge pull request #17 from antonblanchard/writeback-signal Anton Blanchard 2019-09-06 10:09:26 +1000
  • 147b259691 Use a better input signal in writeback Anton Blanchard 2019-09-06 09:46:55 +1000
  • 3f59396907
         Merge pull request #16 from antonblanchard/decode2_rework2 Anton Blanchard 2019-09-04 06:33:40 +1000
  • 5e140298a5 Rework decode2 Anton Blanchard 2019-09-03 12:44:03 +1000
  • d1fdc286c4
         Merge pull request #13 from mikey/dynamic-ranges Anton Blanchard 2019-08-31 13:34:38 +1000
  • 4d5abfb430 Remove dynamic ranges from code Michael Neuling 2019-08-29 09:47:45 +1000
  • 7a85e3877d
         Merge pull request #10 from antonblanchard/arty-fix Anton Blanchard 2019-08-30 09:06:48 +1000
  • 5379b805ec Arty A7 reset pin is C2 Anton Blanchard 2019-08-30 08:39:44 +1000
  • 3819768d2a
         Merge pull request #7 from riktw/fusesoc_arty_a7 Anton Blanchard 2019-08-30 08:38:13 +1000
  • 5aba4e7346
         Merge pull request #9 from antonblanchard/travis-fix Anton Blanchard 2019-08-30 08:26:35 +1000
  • 6c8d28a642 A few Travis CI fixes Anton Blanchard 2019-08-30 08:12:54 +1000
  • 4ebd6fc1f7 Added support for building for Arty A7 boards riktw 2019-08-27 22:20:02 +0200
  • f98370f9e6
         Merge pull request #5 from antonblanchard/travis-test Anton Blanchard 2019-08-29 07:46:51 +1000
  • 2ee269abdb Add an initial travis.yml Anton Blanchard 2019-08-27 10:40:43 +1000
  • 0fd18c2455 Add srd and srw Anton Blanchard 2019-08-28 14:50:11 +1000
  • 73daacbcd4 Add sim only divw Anton Blanchard 2019-08-28 14:07:29 +1000
  • 95b9f19882 Fix ghdl build error with pp_soc_memory Anton Blanchard 2019-08-27 22:12:33 +1000
  • 1fa0b332ca micropython only requires 512kB of BRAM Anton Blanchard 2019-08-27 12:02:00 +1000
  • 1aadee281d
         Merge pull request #6 from mikey/gif Anton Blanchard 2019-08-27 11:50:25 +1000
  • 96787091a6 Add -Wall to CFLAGS Anton Blanchard 2019-08-27 11:44:34 +1000
  • d618171d13 Add pretty gif demo of MicroPython on Microwatt to README.md Michael Neuling 2019-08-27 11:19:15 +1000
  • 7277c6b5ab Add missing argument to fprintf warning Anton Blanchard 2019-08-26 23:11:51 +1000
  • 77f1588a7f Add some initial FPGA synthesis instructions Anton Blanchard 2019-08-26 22:32:15 +1000
  • 0a0ad9b384 Rebuild hello world assuming a 50MHz clock Anton Blanchard 2019-08-26 12:33:15 +1000
  • c036363d8f
         Merge pull request #3 from olofk/plle2 Anton Blanchard 2019-08-26 22:02:17 +1000
  • 12327034d6 Add and use plle2 primitive for nexys boards Olof Kindgren 2019-08-24 11:25:21 +0200
  • 5b2984a15d
         Merge pull request #4 from sharkcz/build Anton Blanchard 2019-08-26 11:33:38 +1000
  • 2d7994dc12 don't cross compile when on Power Dan Horák 2019-08-24 14:02:35 +0200
  • 8bc3e8ea0a Add a simple hello_world example that also echos input Anton Blanchard 2019-08-24 08:59:17 +1000