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b342312e4e tests: mmu: Add tests for instruction translation Paul Mackerras 2020-04-28 16:00:00 +1000
01046527ba MMU: Do radix page table walks on iTLB misses Paul Mackerras 2020-04-28 14:54:22 +1000
3d4712ad43 Add TLB to icache Paul Mackerras 2020-04-27 17:43:19 +1000
882a5a0dc0 tests: Add a test for the MMU radix page table walks Paul Mackerras 2020-04-23 15:33:36 +1000
dee3783d79 MMU: Remove software-loaded dTLB mode Paul Mackerras 2020-05-07 10:17:08 +1000
3eb07dc637 MMU: Refetch PTE on access fault Paul Mackerras 2020-05-06 20:21:01 +1000
f6a0d7f9da MMU: Implement data segment interrupts Paul Mackerras 2020-04-23 21:54:08 +1000
4e6fc6811a MMU: Implement radix page table machinery Paul Mackerras 2020-04-23 15:28:22 +1000
8160f4f821 Add framework for implementing an MMU Paul Mackerras 2020-04-22 11:10:56 +1000
d47fbf88d1 Implement access permission checks Paul Mackerras 2020-04-20 12:43:06 +1000
42d0fcc511 Implement data storage interrupts Paul Mackerras 2020-04-07 16:17:37 +1000
750b3a8e28 dcache: Implement data TLB Paul Mackerras 2020-04-06 17:54:45 +1000
635e316f9b Pass mtspr/mfspr to MMU-related SPRs down to loadstore1 Paul Mackerras 2020-04-22 16:53:39 +1000
3340d8aa9f mw_debug: Add support for reading GSPRs and writing memory Paul Mackerras 2020-05-02 13:31:07 +1000
dd2e71930c debug: Provide a way to examine GPRs, fast SPRs and MSR Paul Mackerras 2020-05-02 13:26:30 +1000
5d282a950c Improve architectural compliance of mfspr and mtspr Paul Mackerras 2020-05-02 20:08:10 +1000
517a91ce5e decode1: Implement eieio as a nop Paul Mackerras 2020-05-02 13:45:39 +1000
8a0a907e2f Implement the extswsli instruction Paul Mackerras 2020-05-02 13:28:19 +1000
8bb3c8f8b6 soc: Add DRAM address decoding Benjamin Herrenschmidt 2019-09-10 18:05:56 +0100
6853d22203 core: Add alternate reset address Benjamin Herrenschmidt 2020-05-07 22:09:59 +1000
982cf166dd litedram: Add basic support for LiteX LiteDRAM Benjamin Herrenschmidt 2019-09-10 18:05:32 +0100
31b55b2a75 core: Improve core reset Benjamin Herrenschmidt 2020-05-08 11:36:37 +1000
fa50df56ef mw_debug: Fix core reset Benjamin Herrenschmidt 2020-05-04 22:16:22 +1000
3687486d36 Update hello_world for 100Mhz clock Benjamin Herrenschmidt 2020-04-30 17:52:11 +1000
0f97b320f6 Change default frequency to 100Mhz Benjamin Herrenschmidt 2019-09-30 14:07:16 +1000
f124dc4a40 xics: Add missing fusesoc core file Benjamin Herrenschmidt 2020-05-08 11:40:39 +1000
8857bd1f58 Add openocd SPI flashing proxies for Arty Joel Stanley 2020-05-06 11:52:12 +0930
1ba29a407a

Merge pull request #166 from paulusmack/master Anton Blanchard 2020-05-07 09:59:19 +1000
102fbcfe9a execute1: Fix interrupt delivery during slow instructions Paul Mackerras 2020-05-04 15:17:04 +1000
fe789190e4 wishbone_debug_master: Fix address auto-increment for memory writes Paul Mackerras 2020-05-01 09:00:21 +1000
102b304db7 Merge remote-tracking branch 'remotes/origin/master' Paul Mackerras 2020-05-06 14:15:22 +1000
4db1676ef8 dcache: Don't assert on dcbz cache hit Paul Mackerras 2020-05-04 08:31:18 +1000
4160f2138d

Merge pull request #165 from mikey/xics Anton Blanchard 2020-05-06 13:27:17 +1000
098c3fbb2b

Merge pull request #167 from tomtor/patch-1 Anton Blanchard 2020-05-01 19:52:59 +1000
c818853a1c Update README.md Tom Vijlbrief 2020-05-01 09:39:49 +0200
cf4dfeca36 Change the default cross compiler prefix to powerpc64le-linux-gnu- Paul Mackerras 2020-04-29 11:37:02 +1000
a05ee9fc7f Makefile: fix typo Paul Mackerras 2020-04-29 11:11:22 +1000
10f4be4309 tests: Add a test for privileged instruction interrupts Paul Mackerras 2020-04-29 09:09:23 +1000
041d6bef60 dcache: Implement the dcbz instruction Paul Mackerras 2020-04-28 18:11:52 +1000
167e37d667 Plumb insn_type through to loadstore1 Paul Mackerras 2020-04-03 14:50:17 +1100
74db071067 execute1: Generate privileged instruction interrupts when MSR[PR] = 1 Paul Mackerras 2020-04-28 19:38:58 +1000
b55c9cc298 execute1: Improve architecture compliance of MSR and related instructions Paul Mackerras 2020-04-28 20:28:20 +1000
f21f9dd5a0

Merge pull request #164 from mikey/tags Anton Blanchard 2020-04-23 19:50:16 +1000
b6bd1ba33d

Merge pull request #163 from paulusmack/excpath Anton Blanchard 2020-04-23 19:49:24 +1000
0076f8bf1d XICS test case Michael Neuling 2020-04-23 14:37:29 +1000
b4f20c20b9 XICS interrupt controller Michael Neuling 2020-04-23 14:36:05 +1000
e5a30a1358 Wire up sim uart TX interrupt Michael Neuling 2020-04-23 14:28:59 +1000
fc5f7506f8 Add calls to dis/enable potato uart IRQ Michael Neuling 2020-04-23 14:28:08 +1000
ff162e42eb Add VHDL TAGS Michael Neuling 2020-04-08 17:35:32 +1000
dc6b1df653 execute1: Don't execute ld/st instruction when taking interrupt Paul Mackerras 2020-04-22 13:54:38 +1000
2b11c81b18

Merge pull request #162 from antonblanchard/bin2hex-removal Anton Blanchard 2020-04-16 18:42:42 +1000
4c2bd76634

Merge pull request #161 from antonblanchard/hello-world-Makefile Anton Blanchard 2020-04-16 18:42:13 +1000
05f4f68c54 rust_lib_demo: Remove bin2hex.py Anton Blanchard 2020-04-16 17:44:17 +1000
afbb99cfd4

Merge pull request #160 from antonblanchard/tomtor-rust-2 Anton Blanchard 2020-04-16 17:40:52 +1000
06b28be577 hello_world: Use Makefile automatic variables Anton Blanchard 2020-04-16 17:38:07 +1000
90ed7adf58 rust_lib_demo: Use common console code Anton Blanchard 2020-04-16 17:14:18 +1000
c37a4c16db rust_lib_demo: Update package dependencies to fix a build error Anton Blanchard 2020-04-16 17:08:15 +1000
ae55f5efbd Add Rust demo Tom Vijlbrief 2020-01-03 10:34:21 +0100
d511e088d2

Merge pull request #159 from shenki/fusesoc-ram-16k Anton Blanchard 2020-04-16 15:15:07 +1000
6a3d2d95df Set default RAM to be 16K in microwatt.core Joel Stanley 2020-04-15 16:06:54 +0930
04b784011a README: hello world needs 16KB of RAM Joel Stanley 2020-04-15 16:02:21 +0930
97e3d47a13

Merge pull request #158 from paulusmack/excpath Anton Blanchard 2020-04-14 12:47:00 +1000
e8a55f900f

Merge pull request #157 from paulusmack/master Anton Blanchard 2020-04-09 11:47:05 +1000
56577827d4 Decode attn in the major opcode decode table Paul Mackerras 2020-04-06 14:07:45 +1000
6f7ef8b1b9 Decode sc in the major opcode decode table Paul Mackerras 2020-04-06 13:24:08 +1000
278ac5e0eb Remove sim_config instruction Paul Mackerras 2020-04-06 13:07:00 +1000
f5f17c24fd execute1: Implement trap instructions properly Paul Mackerras 2020-04-07 20:07:33 +1000
381149b2cc Consolidate trap variants under a single OP_TRAP Paul Mackerras 2020-04-06 12:58:42 +1000
d77033aa92 execute1: Simplify the interrupt logic a little Paul Mackerras 2020-04-07 18:38:18 +1000
fe077a116a Rename OP_MCRF to OP_CROP and trim insn_type_t Paul Mackerras 2020-04-06 12:20:36 +1000
0a95e4bfdd tests: Put an attn instruction at 0x700 Paul Mackerras 2020-04-06 14:09:20 +1000
fb8f3da128 Give exceptions a separate path to writeback Paul Mackerras 2020-04-03 17:02:14 +1100
e990e9c839 tests: Update executables Paul Mackerras 2020-04-03 13:47:20 +1100
c13c73f1ae tests: Adjust header inclusions and Makefile.test Paul Mackerras 2020-04-03 13:46:36 +1100
04ec2115ad hello_world: Use ldcix/stdcix to access UART Paul Mackerras 2020-04-01 15:48:30 +1100
abefafd70b hello_world: Adjust header inclusions and Makefile Paul Mackerras 2020-04-01 15:46:43 +1100
d3291dbdf0

Merge pull request #155 from mikey/exceptions Anton Blanchard 2020-04-03 10:36:36 +1100
9d7df2d507 Add test cases for new exceptions and supervisor state Michael Neuling 2020-03-31 17:32:38 +1100
5ef5604b65 Add sc, illegal and decrementer exceptions and some supervisor state Michael Neuling 2020-03-31 17:32:09 +1100
594a19de37 Plumb attn instruction through to execute1 Michael Neuling 2020-03-25 09:58:18 +1100
96fbd61de8 Breakout the console code so it can be reused. Michael Neuling 2020-03-17 15:25:34 +1100
8bee4ae3cc

Merge pull request #153 from paulusmack/master Anton Blanchard 2020-03-30 13:46:23 +1100
81369187c0 loadstore1: Add support for cache-inhibited load and store instructions Paul Mackerras 2020-03-30 12:39:08 +1100
4e38c2cc21 loadstore1: Move load data formatting from writeback to loadstore1 Paul Mackerras 2020-03-30 09:16:58 +1100
b349cc891a loadstore1: Move logic from dcache to loadstore1 Paul Mackerras 2020-03-28 20:24:13 +1100
cc20989bda

Merge pull request #152 from mikey/gitignore Anton Blanchard 2020-03-11 12:46:01 +1100
ef9c1efd72 dcache: Remove LOAD_UPDATE2 state Paul Mackerras 2020-03-05 15:02:10 +1100
81d777be02 dcache: Trim one cycle from the load hit path Paul Mackerras 2020-03-04 16:20:05 +1100
54a399f162 gitignore: Fix RAM file name Michael Neuling 2020-02-28 15:54:21 +1100
5d85ede97d dcache: Implement load-reserve and store-conditional instructions Paul Mackerras 2020-02-28 08:09:08 +1100
94dd8bc480 dcache: Add support for unaligned loads and stores Paul Mackerras 2020-02-26 11:55:36 +1100
44f53f6bda

Merge pull request #150 from sharkcz/selinux Anton Blanchard 2020-02-23 08:51:33 +1100
1587d9e6eb dcache: Fix obscure bug and minor cleanups Paul Mackerras 2020-02-21 12:34:23 +1100
1a244d3470 Remove single-issue constraint for most loads and stores Paul Mackerras 2020-02-19 15:39:46 +1100
441160d865 execute1: Use truth table embedded in instruction for CR logical ops Paul Mackerras 2020-01-16 13:18:56 +1100
ab50c7710d make the sources volume mount SELinux friendly Dan Horák 2020-01-23 11:37:00 +0100
a2bf039a70

Merge pull request #147 from antonblanchard/diamond-1 Anton Blanchard 2020-01-23 14:36:15 +1100
098f10136d Fix a Diamond issue in decode2 Anton Blanchard 2020-01-23 11:43:25 +1100
0de83edf2e Fix a Diamond build issue in writeback Anton Blanchard 2020-01-23 11:37:24 +1100
39596dc70a

Merge pull request #146 from antonblanchard/vhpi-cleanup Anton Blanchard 2020-01-22 15:15:48 +1100