A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras 58b06eb5f3 decode: Remove const fields from decode_rom_t
The const* fields of decode_rom_t drove multiplexers in decode2 that
picked out various instruction fields and put them into the const*
fields of the Decode2ToExecute1Type record, from where they were
used in execute1.  However, the code in execute1 can just as easily
use the appropriate fields of the original instruction word, since
that is now available in execute1.  This therefore changes the
code to do that, resulting in smaller decode tables.

Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years ago
fpga Improve PLL/MMCM clocks configuration 5 years ago
hello_world Rebuild hello world assuming a 50MHz clock 5 years ago
scripts New C based JTAG debug tool 5 years ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 5 years ago
tests Initial import of microwatt 5 years ago
.gitignore Add new files to git ignore 5 years ago
.travis.yml Allow a full make check on Travis 5 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile decode: Push mtspr/mfspr register decoding down into execute1 5 years ago
README.md Remove gcc software divide patch 5 years ago
common.vhdl decode: Remove const fields from decode_rom_t 5 years ago
core.vhdl Merge branch 'divider' of https://github.com/paulusmack/microwatt 5 years ago
core_debug.vhdl Add core debug module 5 years ago
core_tb.vhdl Add core debug module 5 years ago
cr_file.vhdl Reformat CR file 5 years ago
crhelpers.vhdl Reformat crhelpers, and remove some stale code 5 years ago
decode1.vhdl decode: Remove const fields from decode_rom_t 5 years ago
decode2.vhdl decode: Remove const fields from decode_rom_t 5 years ago
decode_types.vhdl decode: Remove const fields from decode_rom_t 5 years ago
divider.vhdl divider: Do absolute-value ops in divider instead of decode 5 years ago
divider_tb.vhdl divider: Do absolute-value ops in divider instead of decode 5 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 5 years ago
dmi_dtm_tb.vhdl Wishbone debug module 5 years ago
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously 5 years ago
execute1.vhdl decode: Remove const fields from decode_rom_t 5 years ago
execute2.vhdl Reformat execute2 5 years ago
fetch1.vhdl Simplify fetch1 5 years ago
fetch2.vhdl Reformat fetch2 5 years ago
glibc_random.vhdl Reformat glibc_random 5 years ago
glibc_random_helpers.vhdl Reformat glibc_random 5 years ago
helpers.vhdl Reformat helpers 5 years ago
icache.vhdl Add a simple direct mapped icache 5 years ago
icache_tb.vhdl Add an icache testbench 5 years ago
insn_helpers.vhdl Add MCRF instruction 5 years ago
loadstore1.vhdl Reformat loadstore1 5 years ago
loadstore2.vhdl loadstore2: Do data formatting after a register stage 5 years ago
microwatt.core Improve PLL/MMCM clocks configuration 5 years ago
multiply.vhdl Multiply needs to be 16 stages to fix all timing issues 5 years ago
multiply_tb.vhdl Reformat multiply_tb 5 years ago
ppc_fx_insns.vhdl Implement absolute branches 5 years ago
register_file.vhdl Reformat register file 5 years ago
sim_console.vhdl Reformat sim_console 5 years ago
sim_console_c.c Make sim poll non-blocking 5 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket_c.c Add jtag support in simulation via a socket 5 years ago
sim_uart.vhdl Share soc.vhdl between FPGA and sim 5 years ago
simple_ram_behavioural.vhdl Reformat simple_ram_behavioural 5 years ago
simple_ram_behavioural_helpers.vhdl Reformat simple_ram_behavioural 5 years ago
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug 5 years ago
simple_ram_behavioural_tb.bin Initial import of microwatt 5 years ago
simple_ram_behavioural_tb.vhdl Reformat simple_ram_behavioural 5 years ago
soc.vhdl Add core debug module 5 years ago
wishbone_arbiter.vhdl Use a 3 way WB arbiter and cleanup fpga toplevel 5 years ago
wishbone_debug_master.vhdl Wishbone debug module 5 years ago
wishbone_types.vhdl Reformat wishbone code 5 years ago
writeback.vhdl Add a divider unit and a testbench for it 5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)