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Paul Mackerras
7fe84220a5
This aims to simplify the logic between the instruction image and the register file read address ports and reduce the size of the decode tables. With this patch, the input_reg_a column of the decode tables can only select RA or zeroes, the input_reg_b column can only select RB or a constant (0, -1, or an immediate value from the instruction), and the input_reg_c columns can only select RS or zeroes. That means that the rotate/shift/logical ops now have their first input coming in via the input_reg_c column. That means we need to add a read_data3 field to the Decode2ToExecuteType record, but that will go away again when we split out the rotate/mask/logical ops to their own unit. As a related but not tightly connected change, this patch also sets the read1_enable signal to the register file be 0 when RA=0 and the input_reg_a for the instruction is RA_OR_ZERO (previously it was 1). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| fpga | ||
| hello_world | ||
| scripts | ||
| sim-unisim | ||
| tests | ||
| .gitignore | ||
| .travis.yml | ||
| LICENSE | ||
| Makefile | ||
| README.md | ||
| common.vhdl | 5 years ago | |
| core.vhdl | ||
| core_debug.vhdl | ||
| core_tb.vhdl | ||
| cr_file.vhdl | ||
| crhelpers.vhdl | ||
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | ||
| divider_tb.vhdl | ||
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | ||
| execute1.vhdl | 5 years ago | |
| execute2.vhdl | ||
| fetch1.vhdl | ||
| fetch2.vhdl | ||
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| helpers.vhdl | ||
| icache.vhdl | ||
| icache_tb.vhdl | ||
| insn_helpers.vhdl | ||
| loadstore1.vhdl | ||
| loadstore2.vhdl | ||
| microwatt.core | ||
| multiply.vhdl | ||
| multiply_tb.vhdl | ||
| ppc_fx_insns.vhdl | ||
| register_file.vhdl | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_uart.vhdl | ||
| simple_ram_behavioural.vhdl | ||
| simple_ram_behavioural_helpers.vhdl | ||
| simple_ram_behavioural_helpers_c.c | ||
| simple_ram_behavioural_tb.bin | ||
| simple_ram_behavioural_tb.vhdl | ||
| soc.vhdl | ||
| wishbone_arbiter.vhdl | ||
| wishbone_debug_master.vhdl | ||
| wishbone_types.vhdl | ||
| writeback.vhdl | ||
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
- Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)