A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 90b6e27380 Generalize the mul_32bit and mul_signed fields of decode_rom_t This changes the names of the mul_32bit and mul_signed fields of decode_rom_t to is_32bit and is_signed, so they can be used with other types of operations besides multiplies. This plumbs the is_32bit and is_signed flags down into execute1, though they are not used at this point. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 years ago
fpga	Improve PLL/MMCM clocks configuration	5 years ago
hello_world	…
scripts	…
sim-unisim	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	decode: Push mtspr/mfspr register decoding down into execute1	5 years ago
README.md	…
common.vhdl	Generalize the mul_32bit and mul_signed fields of decode_rom_t	5 years ago
core.vhdl	…
core_debug.vhdl	…
core_tb.vhdl	…
cr_file.vhdl	…
crhelpers.vhdl	…
decode1.vhdl	Generalize the mul_32bit and mul_signed fields of decode_rom_t	5 years ago
decode2.vhdl	Generalize the mul_32bit and mul_signed fields of decode_rom_t	5 years ago
decode_types.vhdl	Generalize the mul_32bit and mul_signed fields of decode_rom_t	5 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	Don't reset JTAG request register asynchronously	5 years ago
execute1.vhdl	decode: Avoid multiplexing from instruction reg fields to regfile address ports	5 years ago
execute2.vhdl	…
fetch1.vhdl	…
fetch2.vhdl	Reformat fetch2	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	…
icache.vhdl	…
icache_tb.vhdl	…
insn_helpers.vhdl	Add MCRF instruction	5 years ago
loadstore1.vhdl	…
loadstore2.vhdl	loadstore2: Do data formatting after a register stage	5 years ago
microwatt.core	Improve PLL/MMCM clocks configuration	5 years ago
multiply.vhdl	Multiply needs to be 16 stages to fix all timing issues	5 years ago
multiply_tb.vhdl	…
ppc_fx_insns.vhdl	Implement absolute branches	5 years ago
register_file.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
soc.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	…

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)